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$0,+* PLFURQ &026 *DWH $UUD\
Description
ODTSXExx is a family of 4 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables and
controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXExx
EN
A SL
PADM
EN A PADM
LL
L
LH H
HX
Z
HDL Syntax
Verilog .................... ODTSXExx inst_name (PADM, A, EN);
VHDL...................... inst_name: ODTSXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load)
EN (eq-load)
PADM (pF)
ODTSXE04
2.3
6.9
4.94
Power Characteristics
Cell Output Drive (mA)
ODTSXE04
4
ODTSXE08
8
ODTSXE12
12
ODTSXE16
16
ODTSXE24
24
a. See page 2-15 for power equation.
ODTSXE08
2.3
6.9
4.94
Load
ODTSXE12
2.3
6.9
4.94
ODTSXE16
2.3
6.9
4.94
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
218.9
TBD
240.3
TBD
261.1
TBD
283.9
TBD
302.7
ODTSXE24
2.3
6.9
4.94
4-38