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Description
ODTSXNxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel open-drains (pull-
down) and controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXNxx
A
PADM
A PADM
LL
HZ
Z = High Impedance
HDL Syntax
Verilog .................... ODTSXNxx inst_name (PADM, A);
VHDL...................... inst_name: ODTSXNxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
PADM (pF)
ODTSXN04
8.1
4.90
ODTSXN08
8.1
4.90
Load
ODTSXN12
8.1
4.90
ODTSXN16
8.1
4.90
ODTSXN24
8.1
4.90
Power Characteristics
Cell Output Drive (mA)
ODTSXN04
4
ODTSXN08
8
ODTSXN12
12
ODTSXN16
16
ODTSXN24
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
164.3
TBD
172.6
TBD
180.2
TBD
188.3
TBD
200.2
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODTSXN04
From: A
To: PADM
tZL
3.28
50
8.54
100
15.91
200
30.44
300 (max)
44.81
4-40

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ODTSXN08
Capacitive Load (pF)
From: A
To: PADM
tZL
15
2.02
ODTSXN12
Capacitive Load (pF)
From: A
To: PADM
tZL
15
1.45
ODTSXN16
Capacitive Load (pF)
From: A
To: PADM
tZL
15
1.16
ODTSXN24
Capacitive Load (pF)
From: A
To: PADM
tZL
15
1.03
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
4.79
50
3.36
50
2.62
50
2.00
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
From
A
Delay (ns)
To
PADM
Parameter
tLZ
ODTSXN04
0.80
ODTSXN08
0.93
100
8.62
100
5.94
100
4.58
100
3.34
Cell
ODTSXN12
1.05
200
16.16
200
10.94
200
8.31
200
5.92
300 (max)
23.65
300 (max)
15.84
300 (max)
11.90
300 (max)
8.40
ODTSXN16
1.19
ODTSXN24
1.37
4-41