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Description
ODTSXXxx is a family of 4 to 24 mA, non-inverting, TTL-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol
Truth Table
ODTSXXxx
A SL
PADM
A PADM
LL
HH
HDL Syntax
Verilog .................... ODTSXXxx inst_name (PADM, A);
VHDL...................... inst_name: ODTSXXxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
ODTSXX04
9.3
Power Characteristics
Cell Output Drive (mA)
ODTSXX04
4
ODTSXX08
8
ODTSXX12
12
ODTSXX16
16
ODTSXX24
24
a. See page 2-15 for power equation.
ODTSXX08
9.3
Load
ODTSXX12
9.3
ODTSXX16
9.3
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
198.6
TBD
220.0
TBD
240.8
TBD
263.6
TBD
282.3
ODTSXX24
11.4
4-42

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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODTSXX04
From: A
tPLH
To: PADM tPLH
1.51
3.60
Capacitive Load (pF)
15
ODTSXX08
From: A
tPLH
To: PADM tPLH
1.01
2.19
Capacitive Load (pF)
15
ODTSXX12
From: A
tPLH
To: PADM tPLH
0.97
1.82
Capacitive Load (pF)
15
ODTSXX16
From: A
tPLH
To: PADM tPLH
1.01
1.60
Capacitive Load (pF)
15
ODTSXX24
From: A
tPLH
To: PADM tPLH
1.07
1.31
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
3.44
8.97
50
2.03
5.12
50
1.63
3.72
50
1.52
2.98
50
1.55
2.20
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100
6.21
16.46
100
3.46
9.13
100
2.58
6.37
100
2.22
4.96
100
2.25
3.52
200
11.80
31.17
200
6.29
16.85
200
4.49
11.54
200
3.62
8.83
200
3.65
6.14
300 (max)
17.44
45.68
300 (max)
9.16
24.39
300 (max)
6.41
16.57
300 (max)
5.05
12.60
300 (max)
5.05
8.73
4-43