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Description
ODTXXExx is a family of 1 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables.
Logic Symbol
Truth Table
ODTXXExx
EN
A
PADM
EN A PADM
LL
L
LH
H
HX
Z
Z = High Impedance
HDL Syntax
Verilog .................... ODTXXExx inst_name (PADM, A, EN);
VHDL...................... inst_name: ODTXXExx port map (PADM, A, EN);
Pin Loading
Pin Name
A (eq-load)
EN (eq-load)
PADM (pF)
ODTXXE01
5.6
4.0
4.92
ODTXXE02
7.9
5.3
4.92
ODTXXE04
7.9
5.3
4.93
Load
ODTXXE08
2.3
5.5
4.93
ODTXXE12
2.3
5.5
4.93
ODTXXE16
2.3
5.5
4.93
ODTXXE24
2.3
5.5
4.93
Power Characteristics
Cell
Output Drive
(mA)
ODTXXE01
ODTXXE02
ODTXXE04
ODTXXE08
ODTXXE12
ODTXXE16
ODTXXE24
1
2
4
8
12
16
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
154.9
TBD
164.2
TBD
174.8
TBD
223.0
TBD
243.9
TBD
268.0
TBD
279.9
4-44

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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODTXXE01
From: A
tPLH
To: PADM tPHL
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
2.85
7.15
2.85
7.28
15
ODTXXE02
From: A
tPLH
To: PADM tPHL
1.59
3.67
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
1.75
3.62
15
ODTXXE04
From: A
tPLH
To: PADM tPHL
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
1.02
2.27
1.33
2.68
15
ODTXXE08
From: A
To: PADM
From: EN
To: PADM
tPLH
tPHL
tZH
tZL
1.47
1.55
1.32
1.64
Capacitive Load (pF)
15
ODTXXE12
From: A
tPLH
To: PADM tPHL
From: EN
tZH
To: PADM tZL
Capacitive Load (pF)
1.53
1.73
1.23
1.48
15
ODTXXE16
From: A
tPLH
To: PADM tPHL
1.55
1.87
From: EN
tZH
To: PADM tZL
1.25
1.44
Capacitive Load (pF)
15
ODTXXE24
From: A
To: PADM
From: EN
To: PADM
tPLH
tPHL
tZH
tZL
1.70
1.70
1.31
0.69
25
3.95
10.42
4.03
10.47
50
3.57
9.28
3.77
9.32
50
2.19
5.06
2.36
5.09
50
2.02
2.90
1.82
3.05
50
1.96
2.65
1.67
2.45
50
1.91
2.58
1.64
2.23
50
2.00
2.26
1.68
2.03
4-45
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35
5.07
13.74
5.21
13.71
75
4.97
13.29
5.18
13.36
100
3.66
9.01
3.81
9.03
100
2.76
4.87
2.53
5.01
100
2.48
3.98
2.22
3.77
100
2.36
3.57
2.09
3.27
100
2.39
2.99
2.13
2.78
50
6.76
18.76
6.93
18.69
100
6.37
17.31
6.57
17.37
200
6.47
17.01
6.68
17.08
200
4.19
8.83
3.96
8.94
200
3.46
6.62
3.22
6.42
200
3.14
5.52
2.87
5.27
200
3.15
4.34
2.91
4.11
75 (max)
9.64
27.24
9.67
27.25
150 (max)
9.18
25.37
9.31
25.36
300 (max)
9.36
24.98
9.52
25.00
300 (max)
5.61
12.75
5.39
12.91
300 (max)
4.43
9.22
4.14
9.05
300 (max)
3.85
7.48
3.59
7.22
300 (max)
3.89
5.61
3.60
5.47

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Delay will vary with input conditions. See page 2-17 for interconnect estimates.
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To
Parameter
ODTXXE01 ODTXXE02
EN
PADM
tHZ
tLZ
1.45 1.20
0.41 0.38
ODTXXE04
1.59
0.55
Cell
ODTXXE08
1.24
1.09
ODTXXE12
1.62
1.30
ODTXXE16
2.01
1.60
ODTXXE24
2.01
1.96
4-46