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2'7;;1[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODTXXNxx is a family of 1 to 24 mA, non-inverting, TTL-level, output buffer pieces with N-channel, open-drains (pull-
down).
Logic Symbol
Truth Table
ODTXXNxx
A
PADM
A PADM
LL
HZ
Z = High Impedance
HDL Syntax
Verilog .................... ODTXXNxx inst_name (PADM, A);
VHDL...................... inst_name: ODTXXNxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
PADM (pF)
ODTXXN01
4.3
4.90
ODTXXN02
4.3
4.90
ODTXXN04
4.3
4.91
Load
ODTXXN08
8.3
4.90
ODTXXN12
8.3
4.91
Power Characteristics
Cell
Output Drive
(mA)
ODTXXN01
ODTXXN02
ODTXXN04
ODTXXN08
ODTXXN12
ODTXXN16
ODTXXN24
1
2
4
8
12
16
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
141.7
TBD
143.5
TBD
147.6
TBD
156.9
TBD
163.7
TBD
173.1
TBD
184.9
ODTXXN16
8.3
4.91
ODTXXN24
8.3
4.91
4-47

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Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
ODTXXN01
Capacitive Load (pF)
From: A
To: PADM
tZL
15
6.55
ODTXXN02
Capacitive Load (pF)
From: A
To: PADM
tZL
15
3.25
ODTXXN04
Capacitive Load (pF)
From: A
To: PADM
tZL
15
1.93
ODTXXN08
Capacitive Load (pF)
From: A
To: PADM
tZL
15
1.17
ODTXXN12
Capacitive Load (pF)
From: A
To: PADM
tZL
15
0.99
ODTXXN16
Capacitive Load (pF)
From: A
To: PADM
tZL
15
0.96
ODTXXN24
Capacitive Load (pF)
From: A
To: PADM
tZL
15
0.84
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
25
9.90
50
9.06
50
4.75
50
2.55
50
1.95
50
1.73
50
1.49
35
13.24
75
13.05
100
8.75
100
4.52
100
3.28
100
2.74
100
2.23
50
18.24
100
17.03
200
16.74
200
8.47
200
5.92
200
4.72
200
3.56
75 (max)
26.55
150 (max)
25.12
300 (max)
24.70
300 (max)
12.40
300 (max)
8.56
300 (max)
6.70
300 (max)
4.90
Tristate Timing
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns)
From
To
Parameter
ODTXXN01 ODTXXN02
A
PADM
tLZ
0.23 0.31
ODTXXN04
0.48
Cell
ODTXXN08
0.56
ODTXXN12
0.74
ODTXXN16
1.02
ODTXXN24
1.35
4-48