ODTXXX01.pdf 데이터시트 (총 2 페이지) - 파일 다운로드 ODTXXX01 데이타시트 다운로드

No Preview Available !

2'7;;;[[
®
$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODTXXXxx is a family of 1 to 24 mA, non-inverting, TTL-level output buffer pieces.
Logic Symbol
Truth Table
ODTXXXxx
A
PADM
A PADM
LL
HH
HDL Syntax
Verilog .................... ODTXXXxx inst_name (PADM, A);
VHDL...................... inst_name: ODTXXXxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
ODTXXX01
4.3
ODTXXX02
4.3
ODTXXX04
6.2
Load
ODTXXX08
8.3
ODTXXX12
8.2
Power Characteristics
Cell Output Drive (mA)
ODTXXX01
1
ODTXXX02
2
ODTXXX04
4
ODTXXX08
8
ODTXXX12
12
ODTXXX16
16
ODTXXX24
24
a. See page 2-15 for power equation.
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
149.5
TBD
155.0
TBD
165.6
TBD
189.8
TBD
210.7
TBD
234.8
TBD
248.2
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Capacitive Load (pF)
15
ODTXXX01
From: A
tPLH
To: PADM tPHL
2.52
7.11
25
3.69
10.44
35
4.86
13.76
4-49
ODTXXX16
8.2
50
6.58
18.75
ODTXXX24
10.3
75 (max)
9.33
27.11

No Preview Available !

2'7;;;[[
$0,+*  PLFURQ &026 *DWH $UUD\
Capacitive Load (pF)
15
ODTXXX02
From: A
tPLH
To: PADM tPHL
1.63
3.87
Capacitive Load (pF)
15
ODTXXX04
From: A
tPLH
To: PADM tPHL
1.02
2.18
Capacitive Load (pF)
15
ODTXXX08
From: A
tPLH
To: PADM tPHL
0.91
1.50
Capacitive Load (pF)
15
ODTXXX12
From: A
tPLH
To: PADM tPHL
0.97
1.40
Capacitive Load (pF)
15
ODTXXX16
From: A
tPLH
To: PADM tPHL
1.10
1.59
Capacitive Load (pF)
15
ODTXXX24
From: A
tPLH
To: PADM tPHL
1.05
1.26
Delay will vary with input conditions. See page 2-17 for interconnect estimates.
50
3.59
9.51
50
2.04
4.90
50
1.45
2.87
50
1.37
2.35
50
1.41
2.33
50
1.39
1.80
®
75
4.99
13.53
100
3.46
8.88
100
2.15
4.82
100
1.87
3.66
100
1.80
3.33
100
1.80
2.53
100
6.38
17.54
200
6.31
16.87
200
3.57
8.75
200
2.85
6.27
200
2.58
5.29
200
2.54
3.88
150 (max)
9.20
25.55
300 (max)
9.18
24.84
300 (max)
5.02
12.69
300 (max)
3.84
8.91
300 (max)
3.34
7.24
300 (max)
3.27
5.17
4-50