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Chip Integration Technology Corporation
T0501SA
Ultra-Low Capacitance ESD Protection Device
Features
Applications
Transient protection for high-speed data lines
IEC 61000-4-2 (ESD) ±25kV ( Air)
±22kV ( Contact)
Protects one high-speed data line
Low reverse current:< 10nA typical (VR=5V)
Working voltage: 5V
Low capacitance: 0.25pF typical
HDMI 1.3/1.4 and HDMI 2.0
USB 2.0 and USB 3.0
MHL
LVDS Interfaces
FM Antenna
PCI Express
eSATA Interfaces
Dynamic resistance: 0.90 Ohms (Typ)
Mechanical Characteristics
Solid-state silicon-avalanche technology
DFN0603-2L package
Pb-Free, Halogen Free, RoHS/WEEE Compliant
Nominal Dimensions: 0.6 x 0.3 x 0.25 mm
Lead Finish: NiAu
Description
T0501SA are ultra low capacitance ESD
Molding compound flammability rating: UL 94V-0
Packaging : Tape and Reel
protection devices designed to protect
high speed data interfaces. They are designed
to replace 0201 size mul- tilayer varistors
Circuit Diagram
(MLVs) in portable applications such as cell
I/O_1
phones,notebook computers, and other portable
electronics. This device offers desirable
characteristics for board level protection
including fast response time, low operating
and clamping voltage, and no device degradation.
T0501SA has a typical capacitance of only
0.25pF.This allows it to be used on circuits
operating.
finished with lead-free
T0501SA is in a 2-pin DFN0603 package. It
I/O_2
measures 0.6 x 0.3 mm with a nominal height of
only 0.25mm.Leads are finished with lead-free
NiAu. Each device will protect one line operating
Pin Configuration
at 5 volts. It gives the designer the flexibility to
protect single lines in applications where arrays
are not practical. The combination of small size
and high ESD surge capability makes them
ideal for use in portable applications such as
cellular phones, digital cameras, and Mp3 players.
DFN0603
(Top View)
Document ID : DS-22V02
1
Revised Date : 2016/08/29
Revision : C

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Chip Integration Technology Corporation
T0501SA
Ultra-Low Capacitance ESD Protection Device
Absolute Maximum Rating
Rating
Peak Pulse Power (tp = 8/20μs)
Peak Pulse Current (tp = 8/20μs)
ESD
ESD
per
per
IEC
IEC
61000-4-2
61000-4-2
((ACior)n1tact)1
Operating Temperature
Storage Temperature
Electrical Characteristics (T = 25 °C)
Symbol
Ppk
IPP
VESD
TJ
TSTG
Value
100
4.5
±25
±22
-55 to +125
-55 to +150
Units
Watts
A
kV
°C
°C
Parameter
Symbol
Reverse Stand-Off Voltage
VRWM
Reverse Breakdown Voltage
VBR
Reverse Leakage Current
IR
Conditions
It= 1mA
VRWM = 5V, T=25°C
Minimum
Typical
Maximum
5
Units
V
7 9 10 V
0.005
0.100
μA
Clamping Voltage
VC IPP = 1A, tp = 8/20μs
Clamping Voltage
Dynamic Resistanc2e, 3, 4
Junction Capacitance
VC
RD
Cj
IPP= 4A, tp = 8/20μs
tp = 100ns
VR = 0V, f = 1MHz
0.90
0.25
Notes
1) ESD gun return path connected to ESD ground reference plane.
2) Transmission Line Pulse Test (TLP) Settings: tp= 100ns, tr= 0.2ns,ITLP and VTLP
averaging window: t1 = 70ns to t2= 90ns.
3) Dynamic resistance calculated from I TLP = 4A to I TLP = 16A
4) Guaranteed by design. Not production tested
11 V
15 V
Ohms
0.4 pF
Document ID : DS-22V02
2
Revised Date : 2016/08/29
Revision : C

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Chip Integration Technology Corporation
T0501SA
Ultra-Low Capacitance ESD Protection Device
Clamping Voltage vs. Peak Pulse Current
14
13
12
11
10
9
8
0
Waveform
Parameters:
tr = 8μs
td = 20μs
1234
Peak Pulse Current - IPP (A)
5
Typical Capacitance vs. Reverse Voltage
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
f = 1 MHz
1234
Reverse Voltage - VR (V)
5
5.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
35.0
0.01
Typical Insertion Loss (S21)
0.1 1
Frequency (GHz)
10
ESD Clamping (+8kV Contact per IEC 61000-4-2)
40
Measured with 50 Ohm scope input
impedance, 2GHz bandwidth. Corrected
for 50 Ohm, 40dB a enuator. ESD gun
30 return path connected to ESD ground plane.
TLP Characteristic
30
Transmission Line Pulse Test
(TLP) Se ngs:
25 tp= 100ns, tr= 0.2ns,
ITLP andV TLP averaging window:
t1 = 70ns tot 2 = 90ns
20
15
10
5
0
0 10 20 30 40
TLP Voltage (V)
50
ESD Clamping (-8kV Contact per IEC 61000-4-2)
10
0
20 -10
10
0
-10
-20 -10 0 10 20 30 40 50 60 70 80
Time (ns)
Time (ns)
3
-20
Measured with 50 Ohm scope input
-30 impedance, 2GHz bandwidth. Corrected
for 50 Ohm, 40dB a enuator. ESD gun
return path connected to ESD ground plane.
-40
-20 -10 0 10 20 30 40 50 60 70 80
Time (ns)
Time (ns)
Document ID : DS-22V02
Revised Date : 2016/08/29
Revision : C

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Chip Integration Technology Corporation
T0501SA
Ultra-Low Capacitance ESD Protection Device
Application Information
Assembly Guidelines
The small size of this device means that some care
must be taken during the mounting process to insure
reliable solde joint. The table below provides
CITC recommended assembly guidelines for
Mounting this device. The figure at the right details
CITC recommended aperture based on the
below recommendations. Not that these are only
recommendations and should serve only as a starting
point for design since there are many factors that
affect the assembly process. The exact manufactur-
ing parameters will require some experimentation to
get the desired solder application.
Assembly Parameter
Recommendat ion
Solder Stencil Design
Laser cut, Electro-polished
Aperture shape
Rectangular with rounded
corners
Solder Stencil Thickness 0.100 mm (0.004")
Solder Paste Type
Type 4 size sphere or smaller
Solder Reflow Profile
Per JEDEC J-STD-020
PCB Solder Pad Desig Non-Solder mask defined
PCB Pad Finish
OSP OR NiAu
Recommended Mounting Pattern
Stencil Aperture
Mounting Pad
Package
0.272
0.175
0.250
0.298
0.270
Document ID : DS-22V02
4
Revised Date : 2016/08/29
Revision : C

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Chip Integration Technology Corporation
T0501SA
Ultra-Low Capacitance ESD Protection Device
Ordering Information
Part Number
T0501SA
Qty per
Reel
10,000
Reel
Size
7inch
Carries Tape Specification
A0
0.37 +/-0.03
B0
0.67 +/-0.03
K0
0.32 +/-0.02 mm
Note: All dimensions in mm unless otherwise specified
Device Orientation in Tape
Date Code Location
(Towards Sprocket Holes)
Document ID : DS-22V02
5
Revised Date : 2016/08/29
Revision : C