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Chip Integration Technology Corporation
T0502SK
Ultra-Low Capacitance ESD Protection Device
Features
Transient protection for high-speed data lines
IEC 61000-4-2 (ESD) ±25kV (Air)
±17kV (Contact)
IEC 61000-4-4 (EFT) 40A (5/50 ns)
Cable Discharge Event (CDE)
Small package (2.9mm u 2.8mm u 1.4mm)
Protects two data lines
Low capacitance: 0.3 pF Typical (I/O-GND)
Low leakage current: 0.1μA @ VRWM (Typical)
Low clamping voltage
Each I/O pin can withstand over 1000 ESD
strikes for ±8kV contact discharge
Description
T0502SK is an ultra-low capacitance Transient
Voltage Suppressor (TVS) designed to provide
electrostatic discharge (ESD) protection for high-
speed data interfaces. With typical capacitance of 0.3
pF only, T0502SK is designed to protect parasitic-
sensitive systems against over-voltage and over-
current transient events. It complies with IEC61000-4
-2 (ESD), Level 4 (±15kV air8kV contact discharge
), IEC 61000-4-4 (electrical fast transient - EFT)(40A,
5/50 ns), very fast charged device model (CDM) ESD
and cable discharge event (CDE), etc.
T0502SK uses small SOT23-3L package. Each
T0502SK device can protect two high-speed data lines.
The combined features of low capacitance, small size
and high ESD robustness make T0502SK ideal for
high-speed data ports and high-frequency lines (e.g.,
USB2.0 & DVI) applications. The low clamping voltage
of the T0502SK guarantees a minimum stress on the
protected IC.
1
Applications
Serial ATA
PCI Express
Desktops, Servers and Notebooks
MDDI Ports
USB2.0 Power and Data Line Protection
Display Ports
Digital Visual Interfaces (DVI)
Mechanical Characteristics
SOT23-3L package
Flammability Rating: UL 94V-0
Packaging: Tape and Reel
Circuit Diagram
I/O_2
I/O_1
GND
Pin Configuration
2
1
3
SOT23-3L
(Top View)
Document ID : DS-22V06
Revised Date : 2016/08/29
Revision : C

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Chip Integration Technology Corporation
T0502SK
Ultra-Low Capacitance ESD Protection Device
Absolute Maximum Rating
Symbol
VESD
TOPT
TSTG
Parameter
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
Electrical Characteristics (T = 25oC)
Symbol
Parameter
VRWM
IR
VBR
IT
Nominal Reverse Working Voltage
Reverse Leakage Current @ VRWM
Reverse Breakdown Voltage @ IT
Test Current for Reverse Breakdown
VC
IPP
CESD
Clamping Voltage @ IPP
Maximum Peak Pulse Current
Parasitic Capacitance
VR Reverse Voltage
f Small Signal Frequency
IF Forward Current
VF Forward Voltage @ IF
Value
±25
±17
-55/+125
-55/+150
Units
kV
o
C
o
C
I
IPP
VC VBR VRWM
IIRT
IR
IT
VRWM VBR VC V
IPP
Bi-Directional TVS
Symbol
VRWM
IR
VBR
VC
CESD
CESD
Test Condition
VRWM = 5V, T = 25 oC
Between I/O and GND
IT = 1mA
Between I/O and GND
IPP = 1A, tp = 8/20μs
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and I/O
Minimum Typical Maximum Units
5.0 V
0.1 1.0 μA
7.0 9.0 11.0 V
12.0 V
0.3 0.4 pF
0.3 0.4 pF
Document ID : DS-22V06
Revised Date : 2016/08/29
2 Revision : C

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Chip Integration Technology Corporation
T0502SK
Ultra-Low Capacitance ESD Protection Device
Voltage Sweeping of I/O to GND
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-10 -8 -6 -4 -2 0 2 4 6 8 10
Voltage (V)
Insertion Loss S21 of I/O to GND
5
0
-5
-10
-15
-20
-25
-30
1.00E+06
1.00E+07
1.00E+08
Frenqucy(Hz)
1.00E+09
1.00E+10
Capacitance vs. Voltage of I/O to I/O (f = 1MHz)
Capacitance vs. Reverse Voltage
Normalized Capacitance vs. Reverse Voltage
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
012345
Voltage (V)
ESD Clamping
(+8kV Contact per IEC 61000-4-2)
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
012345
Voltage (V)
ESD Clamping
(-8kV Contact per IEC 61000-4-2)
50
45
40
35
30
25
20
15
10
5
0
-5
-50 0 50 100 150 200
Time (ns)
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-50 0 50 100 150 200
Time (ns)
Document ID : DS-22V06
Revised Date : 2016/08/29
3 Revision : C

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Chip Integration Technology Corporation
T0502SK
Ultra-Low Capacitance ESD Protection Device
Application Information
Pin Connection in PCB
T0502SK is capable to provide ESD protection for
two data lines simultaneously. The pin connevtion
is shown in Figure 1.
Two parallel data lines, from inner IC to I/O port
connector, could connect to T0502SK two I/O pins
directly. Pin 3 of T0502SK is the negative reference
pin, which should connect to the GND of PCB. The
connection wires should be as short as possible in
order to minimize the parasitic inductance.
I/O1
To Connector
I/O2
To Inner IC
21
PCB Layout Guidelines
For optimum ESD protection and the whole circuit
performance, the following PCB layout guidelines are
recommended:
T0502SK GND pin to the PCB GND rail
path should be as short as possible. It could reduce
the ESD transient return path to GND .
The vias connecting T0502SK GND pins to PCB
GND should be wide.
Place T0502SK as close to th connector port as
possible. It could reduce the parasitic inductance
and restrict ESD coupling into adjacent traces.
Avoid running critical signals near board edges.
3
Figure 1 T0502SK pin connection in PCB
Universal Serial Bus ESD Protection
VBUS
USB
Controller
RT
RT
2
CT CT
Figure 2 T0502SK Layout Guidelines
VBUS
D+
D-
GND
1
USB
Port
3
Figure 3 Schematic and Diagram for USB 2.0 Protection using T0502SK
4
Document ID : DS-22V06
Revised Date : 2016/08/29
Revision : C

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Chip Integration Technology Corporation
T0502SK
Ultra-Low Capacitance ESD Protection Device
Package Outline
SOT23-3L package
D
b
SEE VIEW A-A
SECTION B-B
b
e1
e
E1 E
B
B
VIEW A-A
c1 c
θ1 b1
BASE METAL
A4
A3
A A2 GAUGE PLANE
L2
θL
SEATING PLANE
A1
L1
Package Dimensions (Controlling dimensions are in millimeters)
Symbol
A
A1
A2
A3
A4
b
b1
c
c1
D
e
e1
E
E1
L
L1
L2
θ
θ1
Dimensions (mm)
Minimum Typical Maximum
--- --- 1.450
0.000 --- 0.150
0.900
1.200
1.300
0.637
0.787
0.837
0.263
0.413
0.463
0.300 --- 0.500
0.300
0.400
0.450
0.080 --- 0.220
0.080
0.130
0.200
2.90 BSC
1.90 BSC
0.95 BSC
2.80 BSC
1.60 BSC
0.300
0.450
0.600
0.600 REF
0.250 BSC
0o 4o
8o
oo
o
5 10 15
Dimensions (Inches)
Minimum Typical Maximum
--- --- 0.057
0.000 --- 0.006
0.035
0.047
0.012
0.025
0.031
0.033
0.010
0.016
0.018
0.012 --- 0.020
0.012
0.016
0.018
0.003 --- 0.009
0.003
0.005
0.008
0.114 BSC
0.075 BSC
0.037 BSC
0.110 BSC
0.063 BSC
0.012
0.018
0.024
0.024 REF
0.010 BSC
0o 4o
8o
oo
o
5 10 15
Document ID : DS-22V06
Revised Date : 2016/08/29
5 Revision : C