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Chip Integration Technology Corporation
T0506ST
Ultra-Low Capacitance ESD Protection Device
Features
Applications
Transient protection for high-speed data lines
IEC 61000-4-2 (ESD) ±25kV (Air)
±17kV (Contact)
IEC 61000-4-4 (EFT) 40A (5/50 ns)
Cable Discharge Event (CDE)
Package optimized for high-speed lines
Ultra-small package (4.1mmx2.0mmx0.55mm)
Protectssix data lines
Low capacitance: 0.25pF Typical(I/O-GND)
Low leakage current: 0.1uA@V RWM (Typical)
Low clamping voltage
Each I/O pin can withstand over 1000 ESD
strikes for ±8kV contact discharge
Description
Serial ATA
PCI Express
Desktops, Servers and Notebooks
MDDI Ports
USB 2.0/3.0/3.1 Power and Data Line Protection
Display Ports
High Definition Multi-Media Interface (HDMI1.4/2.0)
Digital Visual Interfaces (DVI)
Mechanical Characteristics
DFN4120-10L package
Flammability Rating: UL 94V-0
Packaging: Tape and Reel
T0506ST is an ultra-low capacitance Transient
Voltage Suppressor (TVS) designed to provide
electrostatic discharge (ESD) protection for high-
speed data interfaces. With typical capacitance of
0.25pF only, T0506ST is designed to protect
parasitic-sensitive systems against over-voltage and
over-current transient events. It complies with IEC
61000-4-2 (ESD), Level 4 (±15kV air, ±8kV contact
discharge), IEC 61000-4-4 (electrical fast transien-t -
EFT) (40A,5/50 ns), very fast charged device model
(CDM) ESD and cable discharge event (CDE), etc.
Circuit Diagram
I/O_6 GND
I/O_1 Vcc
Pin Configuration
I/O_2
I/O_5 I/O_4
I/O_3
T0506ST uses ultra-small DFN4120-10L packa. ge.
Each T0506ST device can protect six high-speed
data lines The combined features of ultra-low
capacitance, ultra-small size and high ESD robustness
make T0506ST ideal for high-speed data ports and
high-frequency lines (e.g.,HDMI & DVI) application.s.
The low camping voltage of the T0506ST guarantees
a minimum stress on the protected IC.
GND
10 9
8
76
1 23
Vcc
45
DFN4120-10L
(Top View)
Document ID : DS-22V11
Revised Date : 2016/08/30
1 Revision : C

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Chip Integration Technology Corporation
T0506ST
Ultra-Low Capacitance ESD Protection Device
Absolute Maximum Rating
Symbol
V ESD
TOPT
TSTG
Parameter
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
Electrical Characteristics (T = 25 oC)
Symbol
Parameter
V RWM
IR
VBR
IT
VC
IPP
CESD
VR
f
Nominal Reverse Working Voltage
Reverse Leakage Current @VRWM
Reverse Breakdown Voltage @I T
Test Current for Reverse Breakdown
Clamping Voltage @ I PP
Maximum Peak Pulse Current
Parasitic Capacitance
Reverse Voltage
Small Signal Frequency
IF Forward Current
VF Forward Voltage @IF
Value
±25
±17
-55/+125
-55/+125
Units
kV
oC
oC
I
I PP
VC VBR VRWM
IIRT
IIRT
VRWM VBR VC V
I PP
Bi-Directional TVS
Symbol
V RWM
IR
V BR
VC
CESD
CESD
Test Condition
VRWM = 5V,T = 25 C
Between I/O and GND
IT = 1mA
Between I/O and GND
IPP = 1A, tp= 8/20μs
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and I/O
Minimum
7.0
Typical Maximum
5.0
0.1 1.0
9.0 11.0
12
0.25 0.35
0.25
0.35
Units
V
μA
V
V
pF
pF
Document ID : DS-22V11
Revised Date : 2016/08/30
2 Revision : C

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Chip Integration Technology Corporation
T0506ST
Ultra-Low Capacitance ESD Protection Device
Voltage Sweeping of I/O to GND
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-10 -8 -6 -4 -2 0 2 4 6 8 10
Voltage (V)
Insertion Loss S21 of I/O to GND
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
1.0E+06
1.0E+07
1.0E+08
1.0E+09
Frequency (Hz)
1.0E+10
Capacitance vs. Voltage of I/O to GND (f = 1MHz)
Capacitance vs. Reverse Voltage
Normalized Capacitance vs. Reverse Voltage
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
1234
Reverse Voltage (V)
5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0
1234
Reverse Voltage (V)
5
ESD Clamping of I/O to GND
(+8kV Contact per IEC 61000 -4-2)
ESD Clamping of I/O to GND
(-8kV Contact per IEC 61000-4-2)
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-20.0
-50
0
50 100 150 200
Time (ns)
20.0
10.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-50
0
50 100 150 200
Time (ns)
Document ID : DS-22V11
Revised Date : 2016/08/30
3 Revision : C

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Chip Integration Technology Corporation
T0506ST
Ultra-Low Capacitance ESD Protection Device
Application Information
Pin Connection in PCB
T0506ST provides ESD protection for six data
lines simultaneously. The pin connection is shown
in the figure below.
Four parallel data lines, from inner IC to I/O port
connector, coule connect to T0506ST six I/O pins
directly. Pin 9 of T0506ST is the GND pin, which
should connect to the GND of PCB. The wire should
be as short as possible in order to minimize the
parasitic inductance.
I/O1
To Connector
I/O2
0.1 F
VCC
1
2
3
I/O3
I/O4
To Connector
I/O5
I/O6
4
5
To Inner IC
10
9
GND
8
7
To Inner IC
6
Figure 1 T0506ST pin connection in PCB providing data lines
and power rail line protection.
PCB Layout Guidelines
For optimum ESD protection and the whole circuit
performance, the following PCB layout guidelines are
recommended:
T0506ST GND pin to the PCB GND rail path
should be as short as possible. It could reduce the
ESD transient return path to GND.
The vias connecting T0506ST GND pins to the
PCB GND should be wid.e
Place T0506ST as close to the connector port as
possible. It could reduce the parasitic inductance
and restrict ESD coupling into adjacent traces.
Avoid running critical signals near board edges.
I/O1
To Connector
I/O2
1
VCC floated 2
3
I/O3
I/O4
To Connector
I/O5
I/O6
4
5
To Inner IC
10
9
GND
8
7
To Inner IC
6
Figure 2 T0506ST pin connection in PCB providing data line protection.
VCC pin is left as floating when no VCC rail is presented in PCB.
Document ID : DS-22V11
Revised Date : 2016/08/30
4 Revision : C

No Preview Available !

Chip Integration Technology Corporation
T0506ST
Ultra-Low Capacitance ESD Protection Device
Application Information
Rx+
To Connector
Rx-
1
VBus
2
3
Tx+
Tx-
To Connector
D+
D-
4
5
To Inner IC
10
9
GND
8
7
To inner IC
6
Figure 3 T0506ST pin connection for USB3.0 protection.
Document ID : DS-22V11
Revised Date : 2016/08/30
5 Revision : C