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Chip Integration Technology Corporation
T0514SP
Ultra-Low Capacitance ESD Protection Device
Features
Applications
Transient protection for high-speed data lines
IEC 61000-4-2 (ESD) ±25kV (Air)
±17kV (Contact)
IEC 61000-4-4 (EFT) 40A (5/50 ns)
Cable Discharge Event (CDE)
Package optimized for high-speed lines
Ultra-small package (2.5mmx1.0mmx0.55mm)
Protects four data lines
Low capacitance: 0.40pF Typical(I/O-GND)
Low leakage current: 0.1uA@V RWM (Typical)
Low clamping voltage
Each I/O pin can with stand over 1000 ESD
strikes for ±8kV contact discharge
Description
Serial ATA
PCI Express
Desktops, Servers and Notebooks
MDDI Ports
USB 2.0/3.0/3.1 Power and Data Line Protection
Display Ports
High Definition Multi-Media Interface (HDMI1.4/2.0)
Digital Visual Interfaces (DVI)
Mechanical Characteristics
DFN2510-10L package
Flammability Rating: UL 94V-0
Marking: Part number, Date
Packaging: Tape and Reel
T0514SP is an ultra-low capacitance Transient
Voltage Suppressor (TVS) designed to provide
electrostatic discharge (ESD) protection for high-
speed data interfaces. With typical capacitance of
0.4 pF only, T0514SP is designed to protect
parasitic-sensitive systems against over-voltage and
over-current transient events. It complies with IEC
61000-4-2 (ESD), Level 4 (±15kV air, ±8kV contact
discharge), IEC 61000-4-4 (electrical fast transien-t -
EFT) (40A,5/50 ns), very fast charged device model
(CDM) ESD and cable discharge event (CDE), etc.
Circuit Diagram
I/O_2
I/O_1
GND
Pin Configuration
I/O_4
I/O_3
T0514SP uses ultra-small DFN2510-10L package.
Each T0514SP device can protect four high-speed
data lines The combined features of ultra-low
capacitance, ultra-small size and high ESD robustness
make T0514SP ideal for high-speed data ports and
high-frequency lines (e.g.,HDMI & DVI) application.s.
The low camping voltage of the T0514SP guarantees
a minimum stress on the protected IC.
10 9 8 7 6
12345
I/O_1
I/O_2
GND
I/O_3
I/O_4
DFN2510-10L
(Top View)
Document ID : DS-22V16
Revised Date : 2017/07/20
1 Revision : C

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Chip Integration Technology Corporation
T0514SP
Ultra-Low Capacitance ESD Protection Device
Absolute Maximum Rating
Symbol
IPP
V ESD
TOPT
TSTG
Parameter
Peak Pulse Current(tp=8/20us)(I/O pins)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
Electrical Characteristics (T = 25 oC)
Value
5
±25
±17
-55/+125
-55/+150
Units
A
kV
oC
oC
Symbol
Parameter
VRWM Nominal Reverse Working Voltage
IR Reverse Leakage Current @VRWM
VBR Reverse Breakdown Voltage @I T
IT Test Current for Reverse Breakdown
VC Clamping Voltage @ IPP
IPP Maximum Peak Pulse Current
CESD Parasitic Capacitance
VR Reverse Voltage
f Small Signal Frequency
IF Forward Current
VF Forward Voltage @IF
Current
IF
vF vBRvRWM
IR vF
IT
IPP
Uni-Directional TVS
Symbol
V RWM
IR
V BR
VC
CESD
CESD
Test Condition
VRWM = 5V,T = 25 C
Between I/O and GND
IT = 1mA
Between I/O and GND
IPP = 1A, tp= 8/20μs
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and I/O
2
Minimum
6.0
Typical Maximum
5.0
0.1 1.0
8.0 10.0
12
0.4 0.5
0.05
0.08
Units
V
μA
V
V
pF
pF
Document ID : DS-22V16
Revised Date : 2017/07/20
Revision : C

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Chip Integration Technology Corporation
T0514SP
Ultra-Low Capacitance ESD Protection Device
Voltage Sweeping of I/O to GND
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-2 -1 0 1 2 3 4 5 6 7 8 9
Voltage (V)
Insertion Loss S21 of I/O to GND
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
1.0E+06
1.0E+07
1.0E+08
1.0E+09
Frequency (Hz)
1.0E+10
Capacitance vs. Voltage of I/O to GND (f = 1MHz)
Capacitance vs. Reverse Voltage
Normalized Capacitance vs. Reverse Voltage
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
12 3 4
Reverse Voltage (V)
5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0
12 34
Reverse Voltage (V)
5
ESD Clamping of I/O to GND
(+8kV Contact per IEC 61000-4-2)
ESD Clamping of I/O to GND
(-8kV Contact per IEC 61000-4-2)
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-20.0
-50
0
50 100 150 200
Time (ns)
20.0
10.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-50
0
50 100 150 200
Time (ns)
Document ID : DS-22V16
Revised Date : 2017/07/20
3 Revision : C

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Chip Integration Technology Corporation
T0514SP
Ultra-Low Capacitance ESD Protection Device
Application Information
Pin Connection in PCB
T0514SP provides ESD protection for four data
lines simultaneously. The pin connection is shown
in the figure below.
Four parallel data lines, from inner IC to I/O port
connector, coule connect to T0514SP four I/O pins
directly. Pin 3&8 of T0514SP is the GND pin, which
should connect to the GND of PCB. The wire should
be as short as possible in order to minimize the
parasitic inductance.
To I/O Port
Connector
Date lines
I/O1
I/O2
To Inner IC
Date lines
PCB Layout Guidelines
For optimum ESD protection and the whole circuit
performance, the following PCB layout guidelines are
recommended:
T0514SP GND pin to the PCB GND rail path
should be as short as possible. It could reduce the
ESD transient return path to GND.
The vias connecting T0514SP GND pins to the
PCB GND should be wid.e
Place T0514SP as close to the connector port as
possible. It could reduce the parasitic inductance
and restrict ESD coupling into adjacent traces.
Avoid running critical signals near board edges.
GND
To I/O Port
Connector
Date lines
I/O3
I/O4
To Inner IC
Date lines
Figure 1 T0514SP pin connection in PCB
Document ID : DS-22V16
Revised Date : 2017/07/20
4 Revision : C

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Chip Integration Technology Corporation
T0514SP
Ultra-Low Capacitance ESD Protection Device
Application Information
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D0+
TMDS_D0-
TMDS_CLK+
TMDS_CLK-
CEC
SCL
SDA
HTP_D
TMDS_D2+
T0514SP
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D0+
T0514SP
TMDS_D0-
TMDS_CLK+
T0514TL
TMDS_CLK-
CEC
NC
SCL
SDA
GND
+5V
HTP_D
Figure 2 Layout Top View for HDMI Interface With T0514SP & T0514TL
Document ID : DS-22V16
Revised Date : 2017/07/20
5 Revision : C