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Chip Integration Technology Corporation
T0534VL
Low Capacitance ESD Protection Device
Features
Transient protection for high-speed data lines
IEC 61000-4-2 (ESD) ±25kV (Air)
±17kV (Contact)
IEC 61000-4-4 (EFT) 40A (5/50 ns)
Cable Discharge Event (CDE)
Small package (2.9mm x 2.8mm x 1.4mm)
Protects four data lines
Low capacitance: 0.6pF Typical (I/O-GND)
Low leakage current: 0.1uA@VRWM (Typical)
Low clamping voltage
Each I/O pin can withstand over 1000 ESD
strikes for ±8kV contact discharge
Green part
Description
T0534VL is an ultra-low capacitance Transient
Voltage Suppressor (TVS) designed to provide
electrostatic discharge (ESD) protection for high-
speed data interfaces. With typical capacitance of
0.5pF only, T0534VL is designed to protect parasitic
-sensitive system against over-voltage and over-current
transient events. It complies with IEC61000-4-2(ESD)
,Level X (±25kV air,±17kV contact discharge),IEC
61000-4-4 (electrical fast transient - EFT) (40A,5/50ns)
, very fast charged divice model (CDM)ESD and cable
discharge event (СВE),etc.
T0534VL user SOT23-6L package. Each
T0534VL device can protect four high-speed data
lines. The combined features of low capacitance, small
size and high ESD robustness make T0534VL ideal
for high-speed data ports and high-frequency lines
(e.g., HDMI & DVI) applications. The low clamping
voltage of the T0534 VL guarantees a minimum stress
on the protected IC.
1
Applications
Serial ATA
PCI Express
Desktops, Servers and Notebooks
MDDI Ports
USB 2.0/3.0 Power and Data line Protection
Display Ports
High Definition Multi-Media Interface (HDMI)
Digital Visual Interfaces (DVI)
Mechanical Characteristics
SOT23-6L package
Flammability Rating: UL 94V-0
Marking: Part number
Packaging: Tape and Reel
Circuit Diagram
I/O_2
VCC
I/O_4
I/O_1
GND
Pin Configuration
I/O_2
6
VCC
5
I/O_3
I/O_4
4
123
I/O_1
GND
I/O_3
SOT23-6L
(Top View)
Document ID : DS-22V21
Revised Date : 2017/07/20
Revision : C

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Chip Integration Technology Corporation
T0534VL
Low Capacitance ESD Protection Device
Absolute Maximum Rating
Symbol
IPP
V ESD
TOPT
TSTG
TLST
Parameter
Peak Pulse Current(tp=8/20us)(I/O pins)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Operating Temperature
Storage Temperature
Lead Soldering Temperature
Value
4.5
±25
±17
-55/+125
-55/+150
260
Units
A
kV
oC
oC
oC
Electrical Characteristics (T = 25 oC)
Symbol
Parameter
V RWM
IR
VBR
Nominal Reverse Working Voltage
Reverse Leakage Current @VRWM
Reverse Breakdown Voltage @I T
IT Test Current for Reverse Breakdown
VC Clamping Voltage @ IPP
IPP Maximum Peak Pulse Current
CESD Parasitic Capacitance
VR Reverse Voltage
f Small Signal Frequency
IF Forward Current
VF Forward Voltage @IF
Symbol
Test Condition
V RWM
IR
V BR
VC
CESD
CESD
VRWM = 5V,T = 25 C
Between I/O and GND
IT = 1mA
Between I/O and GND
IPP = 1A, tp= 8/20μs
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and GND
VR = 0V, f = 1MHz
Between I/O and I/O
2
Current
IF
vF vBRvRWM
IR vF
IT
IPP
Uni-Directional TVS
Minimum Typical Maximum Units
5.0 V
0.1 1.0 μA
6.0 8.0 10.0 V
12 V
0.6 0.8 pF
0.05 0.08 pF
Document ID : DS-22V21
Revised Date : 2017/07/20
Revision : C

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Chip Integration Technology Corporation
T0534VL
Low Capacitance ESD Protection Device
Voltage Sweeping of I/O to GND
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-2 -1 0 1 2 3 4 5 6 7 8 9
Voltage (V)
Insertion Loss S21 of I/O to GND
5.0
0.0
-5.0
-10.0
-15.0
-20.0
-25.0
-30.0
1.0E+06
1.0E+07
1.0E+08
Frequency (Hz)
1.0E+09
1.0E+10
Capacitance vs. Voltage of I/O to GND (f = 1MHz)
Capacitance vs. Reverse Voltage
Normalized Capacitance vs. Reverse Voltage
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
12 34
Reverse Voltage (V)
5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0
1234
Reverse Voltage (V)
5
ESD Clamping of I/O to GND
(+8kV Contact per IEC 61000-4-2)
ESD Clamping of I/O to GND
(-8kV Contact per IEC 61000-4-2)
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-20.0
-50 0 50 100 150 200
Time (ns)
20.0
10.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-50 0 50 100 150 200
Time (ns)
Document ID : DS-22V21
Revised Date : 2017/07/20
3 Revision : C

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Chip Integration Technology Corporation
T0534VL
Low Capacitance ESD Protection Device
Application Information
Pin Connection in PCB
T0534VL is capable to provide ESD protection for
four data lines simultaneously. The pin connection is
shown in Figure 1.
Four parallel data lines, from inner IC to I/O port
connector, could connect to T0534VL four I/O pins
directly. Pin 2 of T0534VL is the negative reference
pin, which should connect to the GND of PCB. The
connection wires should be as short as possible in
order to minimize the parasitic inductance.
I/O1
To Connector
To Inner IC
I/O2
PCB Layout Guidelines
For optimum ESD protection and the whole circuit
performance, the following PCB layout guidelines are
recommended:
T0534VL GND pin to the PCB GND rail path
should be as short as possible. It could reduce the
ESD transient return path to GND.
The vias connecting T0534VL VCC & GND pins
to the PCB VCC & GND should be wide.
Place T0534VL as close to the connector port as
possible. It could reduce the parasitic inductance
and restrict ESD coupling into adjacent traces.
Avoid running critical signals near board edges.
GND
VCC
I/O3
To Connector
I/O4
To Inner IC
Figure 1 T0534VL pin connection in PCB
Figure 2 T0534VL Layout Guideline
Universal Serial Bus ESD Protection
VBUS
RT
RT
USB
Controller
CT
CT
CT
CT
654
T0534VL
123
GND
RT
RT
VBUS
D+
USB
D- Port1
GND
VBUS
D+
USB
D- Port2
GND
Document ID : DS-22V21
Revised Date : 2017/07/20
4 Revision : C

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Chip Integration Technology Corporation
T0534VL
Low Capacitance ESD Protection Device
Application Information
TMDS_D2+
TMDS_D2-
T0534VL
TMDS_D2+
TMDS_D2-
TMDS_D1+
TMDS_D1-
TMDS_D0+
TMDS_D0-
T0534VL
TMDS_D1+
TMDS_D1-
TMDS_D0+
TMDS_D0-
TMDS_CLK+
TMDS_CLK-
CEC
TMDS_CLK+
TMDS_CLK-
CEC
NC
DDC_CLK
DDC_DAT
GND
+5V
HOTPLUG_DET
Layout Top View for HDMI Interface with T0534VL
Document ID : DS-22V21
Revised Date : 2017/07/20
5 Revision : C