DS1645AB.pdf 데이터시트 (총 12 페이지) - 파일 다운로드 DS1645AB 데이타시트 다운로드

No Preview Available !

DS1645Y/AB
DS1645Y/AB
Partitionable 1024K NV SRAM
FEATURES
10 years minimum data retention in the absence of
external power
Data is automatically protected during power loss
Directly replaces 128K x 8 volatile static RAM
Write protects selected blocks of memory when pro-
grammed
Unlimited write cycles
Low–power CMOS
Read and write access times as fast as 70 ns
Lithium energy source is electrically disconnected to
retain freshness until power is applied for the first time
Full +10% VCC operating range (DS1645Y)
Optional +5% VCC operating range (DS1645AB)
Optional industrial temperature range of –40°C to
+85°C, designated IND
JEDEC standard 32–pin DIP package
Low Profile Module (LPM) package
– Fits into standard 68–pin PLCC surface mount-
able socket
– 250 mil package height
– Power Fail Output (PFO) warns system of
impending VCC power failure
PIN ASSIGNMENT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 NC
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
32–PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
NC
A15
A16
PFO
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1 34
2 33
3 32
4 31
5 30
6 29
7 28
8 27
9 26
10 25
11 24
12 23
13 22
14 21
15 20
16 19
17 18
34–PIN LOW PROFILE MODULE (LPM)
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
041497 1/12

No Preview Available !

DS1645Y/AB
PIN DESCRIPTION
A0 – A16
– Address Inputs
DQ0 – DQ7 – Data In/Data Out
CE – Chip Enable
WE – Write Enable
OE – Output Enable
PFO
– Power Fail Output (LPM only)
VCC
GND
– Power (+5V)
– Ground
NC – No Connect
DESCRIPTION
The DS1645 1024K Nonvolatile SRAMs are
1,048,576–bit, fully static, nonvolatile SRAMs orga-
nized as 131,072 words by 8 bits. Each NV SRAM has a
self-contained lithium energy source and control cir-
cuitry which constantly monitors VCC for an out–of–tol-
erance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. In addition, the device has the ability to
unconditionally write protect blocks of memory so that
inadvertent write cycles do not corrupt programs and
important data. There is no limit on the number of write
cycles that can be executed and no additional support
circuitry is required for microprocessor interfacing.
DIP–package DS1645 devices can be used in place of
existing 128K x 8 SRAMs directly conforming to the pop-
ular bytewide 32–pin DIP standard. DS1645 devices in
the Low Profile Module package are specifically
designed for surface mount applications. DS1645 LPM
devices also have an additional pin, a Power Fail Out-
put, that can be used to warn a system of impending
VCC power failure.
READ MODE
The DS1645 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The
unique address specified by the 17 address inputs (A0 -
A16) defines which of the 131,072 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within tACC (Access Time) after the last
address input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access
times are not satisfied, then data access must be mea-
sured from the later occurring signal (CE or OE) and the
limiting parameter is either tCO for CE or tOE for OE rather
than address access.
WRITE MODE
The DS1645 devices execute a write cycle whenever
the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling
edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising
edge of CE or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high
state for a minimum recovery time (tWR) before another
cycle can be initiated. The OE control signal should be
kept inactive (high) during write cycles to avoid bus con-
tention. However, if the output drivers are enabled (CE
and OE active) then WE will disable the outputs in tODW
from its falling edge.
DATA RETENTION MODE
The DS1645AB provides full functional capability for
VCC greater than 4.75 volts and write protects by 4.5
volts. The DS1645Y provides full functional capability
for VCC greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of VCC without
any additional support circuitry. The nonvoltile static
RAMs constantly monitor VCC. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As VCC falls below
approximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when VCC rises above approximately
3.0 volts, the power switching circuit connects external
VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds
4.75 volts for the DS1645AB and 4.5 volts for the
DS1645Y.
041497 2/12

No Preview Available !

DS1645Y/AB
FRESHNESS SEAL
Each DS1645 is shipped from Dallas Semiconductor
with its lithium energy source disconnected, guarantee-
ing full energy capacity. When VCC is first applied at a
level greater than VTP, the lithium energy source is
enabled for battery backup operation.
PARTITION PROGRAMMING MODE
The register controlling the partitioning logic is selected
by recognition of a specific binary pattern which is sent
on address lines A13 – A16. These address lines are
the four upper order address lines being sent to RAM.
The pattern is sent by 20 consecutive read cycles with
the exact pattern as shown in Table 1. Pattern matching
must be accomplished using read cycles; any write
cycles will reset the pattern matching circuitry. If this
pattern is matched perfectly, then the 21st through 24th
read cycles will load the partition register. Since there
are 16 protectable partitions, the size of each partition is
128K/16 or 8K x 8. Each partition is represented by one
of the 16 bits contained in the 21st through 24th read
cycles as defined by A13 through A16 and shown in
Table 2. A logical 1 in a bit location write protects the cor-
responding partition. A logical 0 in a bit location dis-
ables write protection. For example, if during the pattern
match sequence bit 22 on address pin A14 was a 1, this
would cause the partition register location for partition 5
to be set to a 1. This in turn would cause the DS1645
devices to internally inhibit WE for all write accesses
where A16 A15 A14 A13=0101. Note that while pro-
gramming the partition register, data which is being
accessed from the RAM should be ignored, since the
purpose of the 24 read cycles is to program the partition
register, not to access data from RAM.
041497 3/12

No Preview Available !

DS1645Y/AB
PATTERN MATCH TO WRITE PARTITION REGISTER Table 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A13 1 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 X X X X
A14 1 1 1 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 X X X X
A15 1 1 1 1 0 0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 X X X X
A16 1 1 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 X X X X
FIRST BITS ENTERED
LAST BITS ENTERED
PARTITION REGISTER MAPPING Table 2
Address
Pin
Bit number in pat-
tern match
sequence
Partition Number
A13 BIT 21
PARTITION 0
A14 BIT 21
PARTITION 1
A15 BIT 21
PARTITION 2
A16 BIT 21
PARTITION 3
A13 BIT 22
PARTITION 4
A14 BIT 22
PARTITION 5
A15 BIT 22
PARTITION 6
A16 BIT 22
PARTITION 7
A13 BIT 23
PARTITION 8
A14 BIT 23
PARTITION 9
A15 BIT 23
PARTITION 10
A16 BIT 23
PARTITION 11
A13 BIT 24
PARTITION 12
A14 BIT 24
PARTITION 13
A15 BIT 24
PARTITION 14
A16 BIT 24
PARTITION 15
Address State Affected
(A16 A15 A14 A13)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
041497 4/12

No Preview Available !

DS1645Y/AB
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
0°C to 70°C, –40°C to +85°C for IND parts
–40°C to +70°C, –40°C to +85°C for IND parts
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(tA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
DS1645Y Power Supply Voltage
DS1645AB Power Supply Voltage
Logic 1
Logic 0
VCC
VCC
VIH
VIL
4.5
4.75
2.2
0.0
5.0
5.0
5.5
5.25
VCC
+0.8
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Input Leakage Current
I/O Leakage Current
CE > VIH < VCC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE = 2.2V
Standby Current CE = VCC - 0.5V
Operating Current
Write Protection Voltage
(DS1645Y)
IIL
IIO
IOH
IOL
ICCS1
ICCS2
ICCO1
VTP
Write Protection Voltage
(DS1645AB)
VTP
( VCC=5V ± 10% for DS1645Y)
(tA: See Note 10) ( VCC=5V ± 5% for DS1645AB)
MIN
TYP
MAX
UNITS NOTES
–1.0 +1.0 mA
–1.0 +1.0 mA
–1.0 mA
2.0 mA
5.0 10.0 mA
3.0 5.0 mA
85 mA
4.25 4.37
4.5
V
14
4.50 4.62 4.75
V
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
(tA = 25°C)
SYMBOL MIN
TYP
MAX
UNITS NOTES
CIN 5 10 pF
CI/O 5 10 pF
041497 5/12