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SH69P802
OTP 2K 4-bit Micro-controller
Features
SH6610D-Based Single-Chip 4-bit Micro-Controller
OTP ROM: 2K X 16 bits
RAM: 123 X 4 bits
- 35 System Control Register
- 88 Data Memory
Operation voltage:
- fOSC = 30kHz - 4MHz, VDD = 2.4V - 5.5V
- fOSC = 30kHz - 10MHz, VDD = 4.5V - 5.5V
6 CMOS Bi-directional I/O pins
- Built-in pull-up for Input ports excluding PORTA.3
- 5 CMOS push-pull output ports
- 1 CMOS open drain output port (PORTA.3)
8-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Load Timer/Counters (one can switch
to external clock source)
Warm-Up Timer
Powerful Interrupt Sources:
- Timer0 Interrupt
- Timer1 Interrupt
- External Interrupts: PORTA & PORTB (Falling Edge)
Oscillator: (Code option)
- Crystal Oscillator: 32.768kHz, 400kHz - 10MHz
- Ceramic Resonator: 400kHz - 10MHz
- External RC Oscillator: 400kHz - 10MHz
- Internal RC Oscillator: 4MHz ± 2%
- External Clock: 30kHz - 10MHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT and STOP
Reset
- Built-in Watchdog Timer (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR)
Two level Low Voltage Reset (LVR) (code option)
OTP Type/Code Protection
8-pin DIP/SOP/TSSOP package
General Description
SH69P802 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, 2K words of OTPROM, 88
nibbles of data RAM, 8-bit timer/counter, on-chip oscillator clock circuitry, on-chip watchdog timer, low voltage reset function,
support power saving modes to reduce power consumption. The SH69P802 is suitable for small controller application.
Pin Configuration
VDD
OSCI/PORTB.1
OSCO/PORTB.0
RESET/PORTA.3
1
2
3
4
8 GND
7 PORTA.0
6 PORTA.1
5 PORTA.2/T0
1 V1.0

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Block Diagram
SH69P802
RAM
35 X 4 Bits
System Register
RAM
88 X 4 Bits
Data Memory
OTP ROM
2048 X 16 Bits
VDD
GND
Power Circuit
WDT RC
Watchdog
Timer
CPU
TIMER 0
Oscillator
PORTB (2-Bits)
PORTA (4-Bits)
OSCO/PORTB.0
OSCI/PORTB.1
PORTA.0
PORTA.1
PORTA.2/T0
RESET/PORTA.3
Reset Circuit
TIMER 1
2

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SH69P802
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
Total 8 pins.
Designation
VDD
OSCI
/PORTB.1
OSCO
/PORTB.0
RESET
/PORTA.3
PORTA.2
/T0
PORTA.1
PORTA.0
GND
I/O Description
P Power supply pin
I
Oscillator input pin, connect to crystal/ceramic oscillator or external
resistor of RC oscillator.
I/O Bit programmable I/O
O Oscillator output pin, connect to crystal/ceramic oscillator
I/O Bit programmable I/O
I Reset pin input (active low, Schmitt trigger input)
I/O
Input port and open drain output. It should be connected with pull-up
resistor if high level is needed to be output.
I/O Bit programmable I/O
I T0 input
I/O Bit programmable I/O
I/O Bit programmable I/O
P Ground pin
OTP Programming Pin Description (OTP Program Mode)
Pin No.
1
4
8
5
7
Symbol
VDD
VPP
GND
SCK
SDA
I/O
P
P
P
I
I/O
Shared by
VDD
RESET
/PORTA.3
GND
PORTA.2/T0
PORTA.0
Description
Programming Power supply (+5.5V)
Programming high voltage Power supply (+11.0V)
Ground
Programming Clock input pin
Programming Data pin
3

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SH69P802
Functional Description
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bits:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can only address 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service
or Call instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The Table Branch Register
(TBR) and Accumulator (AC) is placed by an offset address
in program ROM. TJMP instruction branch into address
((PC11 - PC8) X (28) + (TBR, AC)). The address is
determined by RTNW to return look-up value into (TBR, AC).
ROM code bit7-bit4 is placed into TBR and bit3-bit0 into AC.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bits), DPM
(3-bits) and DPL (4-bits). The addressing range can have
3FFH locations. Pseudo index address (INX) is used to read
or write Data memory, then RAM address bit9 - bit0 comes
from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 8 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC with the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU enters STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $022
Data memory: $028 - $07F
2.2. Configuration of System Register
Address
$00
$01
$02
$03
$04
$05
$06
Bit 3
0
-
T0E
T1GO
T0L.3
T0H.3
T1L.3
Bit 2
IET0
IRQT0
T0M.2
T1M.2
T0L.2
T0H.2
T1L.2
Bit 1
IET1
IRQT1
T0M.1
T1M.1
T0L.1
T0H.1
T1L.1
Bit 0
IEPC
IRQPC
T0M.0
T1M.0
T0L.0
T0H.0
T1L.0
R/W
Remarks
R/W
Interrupt enable flags register
Bit3: Reserved, need to be cleared
R/W Interrupt request flags register
R/W
Bit2-0: Timer0 Mode register
Bit3: T0 signal edge register
R/W
Bit2-0: Timer1 Mode register
Bit3: Set Timer1 on register
R/W Timer0 load/counter low nibble register
R/W Timer0 load/counter high nibble register
R/W Timer1 load/counter low nibble register
4

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SH69P802
Configuration of System Register (continued):
Address
$07
Bit 3
T1H.3
Bit 2
T1H.2
Bit 1
T1H.1
Bit 0
T1H.0
R/W Remarks
R/W Timer1 load/counter high nibble register
$08
PA.3
PA.2
PA.1
PA.0 R/W PORTA data register
$09 -
-
PB.1
PB.0 R/W PORTB data register
$0A
IEP -
- R/W Bit2: Port Interrupt Enable register
$0B
IRQP
-
- R/W Bit2: Port Interrupt Request register
$0C - - - - - Reserved
$0D - - - - - Reserved
$0E
TBR.3
TBR.2
TBR.1
TBR.0 R/W Table branch register
$0F
INX.3
INX.2
INX.1
INX.0 R/W Pseudo index register
$10
DPL.3
DPL.2
DPL.1
DPL.0 R/W Data pointer for INX low nibble register
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble register
$12 - DPH.2 DPH.1 DPH.0 R/W Data pointer for INX high nibble register
$13 - - - - - Reserved
$14
PIN3F.1
PIN3F.0
PIN2F.1
PIN2F.0
R/W
Bit1-0: Pin2 application configuration register
Bit3-2: Pin3 application configuration register
$15 PIN5F.1 PIN5F.0
-
PIN4F
R/W
Bit0: Pin4 application configuration register
Bit3-2: Pin5 application configuration register
$16
PIN7F.1
PIN7F.0
PIN6F.1
PIN6F.0
R/W
Bit1-0: Pin6 application configuration register
Bit3-2: Pin7 application configuration register
$17 - - - - - Reserved
$18 PACR.3 PACR.2 PACR.1 PACR.0 R/W PORTA input/output control register
$19 -
- PBCR.1 PBCR.0 R/W PORTB input/output control register
$1A - - - - - Reserved
$1B - - - - - Reserved
$1C - - - - - Reserved
$1D - - - - - Reserved
$1E
-
WDT
WDT.2
-
WDT.1
-
WDT.0 R/W Bit2-0: Watchdog timer control register
- R Bit3: Watchdog timer overflow flag register
$1F - - - - - Reserved
$20 - - - - - Reserved
$21 - - - - - Reserved
$22 - - - - - Reserved
* Please refer to SH6610C user’s manual for more detailed information of System Register.
3. ROM
The ROM can address 2048 X 16 bits of program area from $000 to $7FF.
3.1. Vector Address Area ($000 to $004)
The program is sequentially executed. There is an area address $000 through $004 that is reserved for a special interrupt
service routine such as starting vector address.
Address
Instruction
$000
JMP*
$001
-
$002
JMP*
$003
JMP*
$004
JMP*
* JMP instruction can be replaced by any instruction.
Remarks
Jump to Reset service routine
Reserved
Jump to Timer0 interrupt service routine
Jump to Timer1 interrupt service routine
Jump to PORTA/B interrupt service routine
5