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SH69P461
OTP 2K 4-bit Micro-controller with 8-bit SAR A/D Converter
Features
SH6610D-Based Single-Chip 4-bit Micro-Controller With
8-bit SAR A/D Converter
OTPROM: 2K X 16 bits
RAM: 123 X 4 bits
- 35 System Control Register
- 88 Data Memory
Operation voltage:
- fOSC = 30kHz - 4MHz, VDD = 2.4V - 5.5V
- fOSC = 30kHz - 10MHz, VDD = 4.5V - 5.5V
6 CMOS Bi-directional I/O pins
- Built-in pull-up for Input ports excluding PORTA3
- 5 CMOS push-pull output ports
- 1 CMOS open drain output port (PORTA.3)
8-Level Stack (Including Interrupts)
Two 8-bit Auto Re-Load Timer/Counters (one can switch
to external clock source)
Warm-Up Timer
Powerful Interrupt Sources:
- Timer0 Interrupt
- Timer1 Interrupt
- A/D interrupt
- External Interrupts: PORTA/B (Falling Edge) & Comparator
Output Change Interrupt
Oscillator: (Code option)
- Crystal Oscillator: 32.768kHz, 400kHz - 10MHz
- Ceramic Resonator: 400kHz - 10MHz
- External RC Oscillator: 400kHz - 10MHz
- Internal RC Oscillator: 4MHz ± 2%
- External Clock: 30kHz - 10MHz
Instruction Cycle Time (4/fOSC)
Two Low Power Operation Modes: HALT and STOP
Reset
- Built-in Watchdog Timer (Code Option)
- Built-in Power-on Reset (POR)
- Built-in Low Voltage Reset (LVR)
Two level Low Voltage Reset (LVR) (code option)
5 Channels 8-bit Resolution Analog/Digital Converter (ADC)
Complementary PWM driving for smart DC brush-less fan
One (6+2) bits PWM output, which can output from two ports
controlled by comparator
1 Analog Comparator with Internal Reference
Internal Reliable Reset Circuit
OTP Type/Code Protection
8-pin DIP/SOP/TSSOP package
General Description
SH69P461 is a single-chip 4-bit micro-controller. This device integrates a SH6610D CPU core, 2K words of OTPROM, 88
nibbles of data RAM, 8-bit timer/counter, 8-bit ADC, (6+2) bits high speed PWM output, analog comparator, on-chip oscillator
clock circuitry, on-chip watchdog timer, low voltage reset function, Complementary PWM driving for smart DC brush-less fan
and support power saving modes to reduce power consumption. It is suitable for DC fan application.
Pin Configuration
VDD
OSCI/PORTB.1/AN4/PWMB
OSCO/PORTB.0/AN3/PWM
RESET/PORTA.3/COUT1
1
2
3
4
8 GND
7 PORTA.0/CIN+/AN0
6 PORTA.1/CIN-/AN1/VREF
5 PORTA.2/T0/AN2/COUT0
1 V2.1

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Block Diagram
RAM
35 X 4 Bits
System Register
RAM
88 X 4 Bits
Data Memory
OTP ROM
2048 X 16 Bits
WDT RC
Watchdog
Timer
8 Bits
ADC Circuit
CPU
(6 + 2) Bits
PWM Circuit
VDD
GND
Power Circuit
TIMER 0
TIMER 1
SH69P461
Oscillator
PORTB (2-Bits)
AN4 - AN3
OSCO/PORTB.0/AN3/PWM
OSCI/PORTB.1/AN4/PWMB
PORTA (4-Bits)
COMPARATOR
AN2 - AN0
ADC VREF
Reset Circuit
PORTA.0/CIN+/AN0
PORTA.1/CIN-/AN1/VREF
PORTA.2/T0/AN2/COUT0
RESET/PORTA.3/COUT1
2

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SH69P461
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
Total 8 pins.
Designation
VDD
OSCI
/PORTB.1
/AN4
/PWMB
OSCO
/PORTB.0
/AN3
/PWM
RESET
/PORTA.3
/COUT1
PORTA.2
/T0
/AN2
/COUT0
PORTA.1
/CIN-
/AN1
/VREF
PORTA.0
/CIN+
/AN0
GND
I/O Description
P Power supply pin
I
Oscillator input pin, connect to crystal/ceramic oscillator or external
resistor of RC oscillator.
I/O Bit programmable I/O
I ADC input channel AN4
O PWM output channel2 in Comparator control mode
O Oscillator output pin, connect to crystal/ceramic oscillator
I/O Bit programmable I/O
I ADC input channel AN3
O PWM output channel
I Reset pin input (active low, Schmitt trigger input)
I/O
Input port and open drain output. It should be connected with pull-up
resistor if high level is needed to be output.
O Comparator open-drain output
I/O Bit programmable I/O
I T0 input
I ADC input channel AN2
O Comparator push-pull output
I/O Bit programmable I/O
I Comparator input -
I ADC input channel AN1
I External voltage reference
I/O Bit programmable I/O
I Comparator input +
I ADC input channel AN0
P Ground pin
OTP Programming Pin Description (OTP Program Mode)
Pin No.
1
4
8
5
Symbol
VDD
VPP
GND
I/O
P
P
P
SCK
I
7
SDA
I/O
Shared by
VDD
RESET
/PORTA.3
/COUT1
GND
PORTA.2
/T0
/AN2
/COUT0
PORTA.0
/CIN+
/AN0
Description
Programming Power supply (+5.5V)
Programming high voltage Power supply (+11.0V)
Ground
Programming Clock input pin
Programming Data pin
3

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SH69P461
Functional Description
1. CPU
The CPU contains the following functional blocks: Program
Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY),
Accumulator, Table Branch Register, Data Pointer (INX,
DPH, DPM, and DPL) and Stacks.
1.1. PC
The PC is used for ROM addressing consisting of 12-bits:
Page Register (PC11), and Ripple Carry Counter (PC10,
PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0).
The program counter is loaded with data corresponding to
each instruction. The unconditional jump instruction (JMP)
can be set at 1-bit page register for higher than 2K.
The program counter can only address 4K program ROM.
(Refer to the ROM description).
1.2. ALU and CY
The ALU performs arithmetic and logic operations. The ALU
provides the following functions:
Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
Decimal adjustments for addition/subtraction (DAA, DAS)
Logic operations (AND, EOR, OR, ANDIM, EORIM, ORIM)
Decisions (BA0, BA1, BA2, BA3, BAZ, BC)
Logic Shift (SHR)
The Carry Flag (CY) holds the ALU overflow that the
arithmetic operation generates. During an interrupt service
or Call instruction, the carry flag is pushed into the stack and
recovered from the stack by the RTNI instruction. It is
unaffected by the RTNW instruction.
1.3. Accumulator (AC)
The accumulator is a 4-bit register holding the results of the
arithmetic logic unit. In conjunction with the ALU, data is
transferred between the accumulator and system register, or
data memory can be performed.
1.4. Table Branch Register (TBR)
Table Data can be stored in program memory and can be
referenced by using Table Branch (TJMP) and Return
Constant (RTNW) instructions. The Table Branch Register
(TBR) and Accumulator (A) is placed by an offset address in
program ROM. TJMP instruction branch into address ((PC11
- PC8) X (28) + (TBR, A)). The address is determined by
RTNW to return look-up value into (TBR, A). ROM code
bit7-bit4 is placed into TBR and bit3-bit0 into A.
1.5. Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPH (3-bits), DPM
(3-bits) and DPL (4-bits). The addressing range can have
3FFH locations. Pseudo index address (INX) is used to read
or write Data memory, then RAM address bit9 - bit0 comes
from DPH, DPM and DPL.
1.6. Stack
The stack is a group of registers used to save the contents of
CY & PC (11-0) sequentially with each subroutine call or
interrupt. The MSB is saved for CY and it is organized into 13
bits X 8 levels. The stack is operated on a first-in, last-out
basis and returned sequentially to the PC with the return
instructions (RTNI/RTNW).
Note:
The stack nesting includes both subroutine calls and
interrupts requests. The maximum allowed for subroutine
calls and interrupts are 8 levels. If the number of calls and
interrupt requests exceeds 8, then the bottom of stack will be
shifted out, that program execution may enter an abnormal
state.
2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep data
after the CPU enters STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $022:
Data memory: $028 - $07F
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SH69P461
2.2. Configuration of System Register
Address
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
Bit 3
IEAD
IRQAD
T0E
T1GO
T0L.3
T0H.3
T1L.3
T1H.3
PA.3
-
IEC
IRQC
Bit 2
IET0
IRQT0
T0M.2
T1M.2
T0L.2
T0H.2
T1L.2
T1H.2
PA.2
-
IEP
IRQP
Bit 1
IET1
IRQT1
T0M.1
T1M.1
T0L.1
T0H.1
T1L.1
T1H.1
PA.1
PB.1
-
-
CONMODE CONEN
COUT
DEB OUTINV CINS
TBR.3
INX.3
DPL.3
-
-
-
PIN3F.1
TBR.2
INX.2
DPL.2
DPM.2
DPH.2
-
PIN3F.0
TBR.1
INX.1
DPL.1
DPM.1
DPH.1
-
PIN2F.1
PIN5F.1 PIN5F.0
-
PIN7F.1
VREF3
PACR.3
-
PIN7F.0
VREF2
PACR.2
-
PIN6F.1
VREF1
PACR.1
PBCR.1
Bit 0
IEPC
IRQPC
T0M.0
T1M.0
T0L.0
T0H.0
T1L.0
T1H.0
PA.0
PB.0
-
-
COMEN
REFS
TBR.0
INX.0
DPL.0
DPM.0
DPH.0
-
PIN2F.0
PIN4F
PIN6F.0
VREF0
PACR.0
PBCR.0
R/W
Remarks
R/W Interrupt enable flags
R/W Interrupt request flags
R/W
R/W
R/W
Bit2-0: Timer0 Mode register
Bit3: T0 signal edge
Bit2-0: Timer1 Mode register
Bit3: Set Timer1 on
Timer0 load/counter register low nibble
R/W Timer0 load/counter register high nibble
R/W Timer1 load/counter register low nibble
R/W Timer1 load/counter register high nibble
R/W PORTA
R/W PORTB
R/W
Bit2: Port Interrupt Enable
Bit3: Comparator output change Interrupt Enable
R/W
Bit2: Port Interrupt Request
Bit3: Comparator output change Interrupt Request
Bit0: Set Comparator on
R/W Bit1: Set PWM control by Comparator
R Bit2: PWM control mode select
Bit3: Comparator data bit
Bit0: Set Internal Reference
R/W
Bit1: Select Comparator Input Channel
Bit2: Comparator output Invert control bit
Bit3: Comparator output debounce on/off
R/W Table Branch Register
R/W Pseudo index register
R/W Data pointer for INX low nibble
R/W Data pointer for INX middle nibble
R/W Data pointer for INX high nibble
- Reserved
R/W
Bit0, 1: Pin2 application configuration
Bit2, 3: Pin3 application configuration
R/W
Bit0: Pin4 application configuration
Bit2, 3: Pin5 application configuration
R/W
Bit0, 1: Pin6 application configuration
Bit2, 3: Pin7 application configuration
R/W Internal Voltage Reference for Comparator
R/W PORTA input/output control
R/W PORTB input/output control
*Please refer to SH6610C user’s manual for more detailed information on System Register.
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