IA188ES.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 IA188ES 데이타시트 다운로드

No Preview Available !

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
®
IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
®
IA211050902-19
http://www.innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 1 of 154
1-888-824-4184

No Preview Available !

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
Copyright 2011 by Innovasic Semiconductor, Inc.
Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
AMD, Am186, and Am188 are trademarks of Advanced Micro Devices, Inc.
MILES™ is a trademark of Innovasic Semiconductor, Inc.
®
IA211050902-19
http://www.innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 2 of 154
1-888-824-4184

No Preview Available !

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
TABLE OF CONTENTS
List of Figures ..................................................................................................................................9
List of Tables .................................................................................................................................10
Conventions ...................................................................................................................................13
Acronyms and Abbreviations ........................................................................................................14
1. Introduction...........................................................................................................................15
1.1 General Description.....................................................................................................15
1.2 Features .......................................................................................................................15
2. Packaging, Pin Descriptions, and Physical Dimensions.......................................................16
2.1 Packages and Pinouts ..................................................................................................16
2.1.1 IA186ES TQFP Package ................................................................................17
2.1.2 IA188ES TQFP Package ................................................................................20
2.1.3 TQFP Physical Dimensions............................................................................23
2.1.4 IA186ES PQFP Package.................................................................................24
2.1.5 IA188ES PQFP Package.................................................................................27
2.1.6 PQFP Physical Dimensions ............................................................................30
2.2 Pin Descriptions ..........................................................................................................31
2.2.1 a19/pio9, a18/pio8, a17/pio7, a16a0Address Bus (synchronous
outputs with tristate) .......................................................................................31
2.2.2 ad15ad8 (IA186ES)Address/Data Bus (level-sensitive
synchronous inouts with tristate) ....................................................................31
2.2.3 ao15ao8 (IA188ES)Address Bus (level-sensitive synchronous
outputs with tristate) .......................................................................................31
2.2.4 ad7ad0Address/Data Bus (level-sensitive synchronous inouts with
2.2.5
2.2.6
2.2.7
tristate) ............................................................................................................31
aleAddress Latch Enable (synchronous output) .........................................32
ardyAsynchronous Ready (level-sensitive asynchronous input)................32
bhe_n/aden_n (IA186ES only)Bus High Enable (synchronous
output with tristate)/Address Enable (input with internal pullup) ..................32
2.2.8 clkoutaClock Output A (synchronous output)............................................33
2.2.9 clkoutbClock Output B (synchronous output)............................................33
2.2.10 cts0_n/enrx0_n/pio21Clear-to-Send 0/Enable-Receive-Request 0
(both are asynchronous inputs).......................................................................33
2.2.11 den_n/ds_n/pio5Data Enable /Data Strobe (both are synchronous
outputs with tristate) .......................................................................................34
2.2.12 drq0/int5/pio12DMA Request 0 (synchronous level-sensitive
input)/Maskable Interrupt Request 5 (asynchronous edge-triggered
input)...............................................................................................................34
2.2.13 drq1/int6/pio13DMA Request 1 (synchronous level-sensitive
input)/Maskable Interrupt Request 6 (asynchronous edge-triggered
input)...............................................................................................................34
®
IA211050902-19
http://www.innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 3 of 154
1-888-824-4184

No Preview Available !

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
2.2.14 dt/r_n/pio4Data Transmit or Receive (synchronous output with
tristate) ............................................................................................................34
2.2.15 gndGround ..................................................................................................35
2.2.16 hldaBus Hold Acknowledge (synchronous output)....................................35
2.2.17 int0Maskable Interrupt Request 0 (asynchronous input)............................35
2.2.18 int1/select_nMaskable Interrupt Request 1/Slave Select (both are
asynchronous inputs) ......................................................................................35
2.2.19 int2/inta0_n/pwd/pio31Maskable Interrupt Request 2
(asynchronous input)/Interrupt Acknowledge 0 (synchronous
output)/Pulse Width Demodulator (Schmitt trigger input) .............................36
2.2.20 int3/inta1_n/irqMaskable Interrupt Request 3 (asynchronous
input)/Interrupt Acknowledge 1 (synchronous output)/Interrupt
Acknowledge (synchronous output) ...............................................................36
2.2.21 int4/pio30Maskable Interrupt Request 4 (asynchronous input)..................37
2.2.22 lcs_n/once0_nLower Memory Chip Select (synchronous output
with internal pullup)/ONCE Mode Request (input) .......................................37
2.2.23 mcs0_n/pio14Midrange Memory Chip Select (synchronous output
with internal pullup) .......................................................................................37
2.2.24 mcs2_nmcs1_n (pio24pio 15)Midrange Memory Chip Selects
(synchronous outputs with internal pullup) ....................................................37
2.2.25 mcs3_n/rfsh_n/pio25Midrange Memory Chip Select (synchronous
outputs with internal pullup)/Automatic Refresh (synchronous output) ........38
2.2.26 nmiNonmaskable Interrupt (synchronous edge-sensitive input) ................38
2.2.27 pcs1_npcs0_n (pio17pio16)Peripheral Chip Selects 10
(synchronous outputs).....................................................................................38
2.2.28 pcs2_n/cts1_n/enrx1_n/pio18Peripheral Chip Select 2
(synchronous output)/Clear-to-Send 1 (asynchronous input)/Enable-
Receiver-Request 1 (asynchronous input) ......................................................39
2.2.29 pcs3_n/rts1_n/rtr1_n/pio18Peripheral Chip Select 3 (synchronous
output)/Ready-to-Send 1 (asynchronous output)/Ready-to-Receive 1
(asynchronous input) ......................................................................................39
2.2.30 pcs5_n/A1/pio3Peripheral Chip Select 5 (synchronous
output)/Latched Address Bit [1] (synchronous output) ..................................40
2.2.31 pcs6_n/A2/pio2Peripheral Chip Select 6 (synchronous
output)/Latched Address Bit [2] (synchronous output) ..................................40
2.2.32 pio31pio0Programmable I/O Pins (asynchronous input/output
open-drain)......................................................................................................40
2.2.33 rd_nRead strobe (synchronous output with tristate) ...................................40
2.2.34 res_nReset (asynchronous level-sensitive input)........................................40
2.2.35 rfsh2_n/aden_n (IA188ES only)Refresh 2 (synchronous output
with tristate)/Address Enable (input with internal pullup) .............................41
®
IA211050902-19
http://www.innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 4 of 154
1-888-824-4184

No Preview Available !

IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
2.2.36 rts0_n/rtr0_n/pio20Ready-to-Send 0 (asynchronous output)/Ready-
to-Receive 0 (asynchronous input) .................................................................41
2.2.37 rxd0_n/pio23Receive Data 0 (asynchronous input) ...................................41
2.2.38 rxd1_n/pio28Receive Data 1 (asynchronous input) ...................................41
2.2.39 s2_ns0_nBus Cycle Status (synchronous outputs with tristate) ...............41
2.2.40 s6/lock_n/clkdiv2_n/pio29Bus Cycle Status Bit [6] (synchronous
output)/Bus Lock (synchronous output)/Clock Divide by 2 (input with
internal pullup)................................................................................................42
2.2.41 srdy/pio6Synchronous Ready (synchronous level-sensitive input)............42
2.2.42 tmrin0/pio11Timer Input 0 (synchronous edge-sensitive input) ................42
2.2.43 tmrin1/pio0Timer Input 1 (synchronous edge-sensitive input) ..................43
2.2.44 tmrout0/pio10Timer Output 0 (synchronous output) .................................43
2.2.45 tmrout1/pio1Timer Output 1 (synchronous output) ...................................43
2.2.46 txd0/pio22Transmit Data 0 (asynchronous output) ....................................43
2.2.47 txd1/pio27Transmit Data 1 (asynchronous output) ....................................43
2.2.48 ucs_n/once1_nUpper Memory Chip Select (synchronous
output)/ONCE Mode Request 1 (input with internal pullup) .........................43
2.2.49 uzi_n/pio26Upper Zero Indicate (synchronous output)..............................44
2.2.50 vccPower Supply (input)..............................................................................44
2.2.51 whb_n (IA186ES only)Write High Byte (synchronous output with
tristate) ............................................................................................................44
2.2.52 wlb_n/wb_nWrite Low Byte (IA186ES only) (synchronous output
with tristate)/Write Byte (IA188ES only) (synchronous output with
tristate) ............................................................................................................44
2.2.53 wr_nWrite Strobe (synchronous output) ....................................................44
2.2.54 x1Crystal Input ...........................................................................................44
2.2.55 x2Crystal Input ...........................................................................................44
2.3 Pins Used by Emulators ..............................................................................................45
3. Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................45
4. Device Architecture ..............................................................................................................47
4.1 Bus Interface and Control ...........................................................................................47
4.2 Clock and Power Management ...................................................................................49
4.3 System Clocks .............................................................................................................49
4.4 Power-Save Mode .......................................................................................................50
4.5 Initialization and Reset................................................................................................50
4.6 Reset Configuration Register ......................................................................................50
4.7 Chip Selects.................................................................................................................50
4.8 Chip-Select Timing .....................................................................................................50
4.9 Ready- and Wait-State Programming..........................................................................51
4.10 Chip-Select Overlap ....................................................................................................51
4.11 Upper-Memory Chip Select ........................................................................................52
4.12 Low-Memory Chip Select ...........................................................................................52
®
IA211050902-19
http://www.innovasic.com
UNCONTROLLED WHEN PRINTED OR COPIED
Customer Support:
Page 5 of 154
1-888-824-4184