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True Color VGA Family
CL-GD542X
Technical Reference Manual
© Copyright 1995 — Cirrus Logic Inc. All rights reserved.

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Notice
Cirrus Logic Inc. has made best efforts to ensure that the information contained in this doc-
ument is accurate and reliable. However, the information is subject to change without
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for infringements of patents or other rights of third parties. This document is the property of
Cirrus Logic Inc. and implies no license under patents, copyrights, or trade secrets. No part
of this publication may be copied, reproduced, stored in a retrieval system, or transmitted,
in any form or by any means, electronic, mechanical, photographic, or otherwise, or used
as the basis for manufacture or sale of any items without the prior written consent of Cirrus
Logic Inc. Cirrus Logic, AutoMap, Fair Share, FeatureChips, Good Data, MediaDAC,
MotionVideo, MVA, PicoPower, SimulSCAN, S/LA, SofTarget, UXART, Vision Port, Wave-
Port, WIC, and WindowInterChip are trademarks of Cirrus Logic Inc. Other trademarks in
this document belong to their respective companies. Cirrus Logic Inc. products are covered
by the following U.S. patents: 4,293,783; Re. 31,287; 4,763,332; 4,777,635; 4,839,896;
4,931,946; 4,975,828; 4,979,173; 5,032,981; 5,122,783; 5,131,015; 5,140,595; 5,157,618;
5,179,292; 5,185,602; 5,220,295; 5,241,642; 5,276,856; 5,280,488; 5,287,241; 5,291,499;
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© Copyright 1995 — Cirrus Logic Inc. All rights reserved.
3100 West Warren Ave.
Fremont, CA 94538
(510) 623-8300

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True Color Family Technical Reference Manual
CONTENTS
Revision History
This technical reference manual has been modified to incorporate a new member of the True Color
VGA family, the CL-GD5425. All pertinent information has been added, including:
• Functional descriptions
• Pin diagrams and descriptions
• Bus interface specifications
• Timing considerations
• Register information
• BIOS functions
• Schematics
• TV output support
• Glossary definitions
FOR THE LATEST SCHEMATICS,
PLEASE CONTACT CIRRUS LOGIC.
This document was originally published in May, 1995.
Copyright 1995 — Cirrus Logic Inc.
iii
September 1997

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True Color Family Technical Reference Manual
CONTENTS
Table of Contents
1. INTRODUCTION ..................................................................................... 1-2
1.1 Scope of Document ................................................................................................. 1-2
1.2 Applicable Chip Types ............................................................................................. 1-2
1.3 Intended Audience .................................................................................................. 1-2
1.4 Conventions ............................................................................................................ 1-2
2. OVERVIEW ............................................................................................. 2-2
2.1 Features .................................................................................................................. 2-2
2.2 Chip Architecture ..................................................................................................... 2-4
2.2.1 Host Access to CL-GD542X Registers ........................................................ 2-5
2.2.2 Host Access to Display Memory .................................................................. 2-5
2.2.3 Display Access to Display Memory .............................................................. 2-5
2.2.4 Display Memory Refresh .............................................................................. 2-5
2.3 Major Components .................................................................................................. 2-6
2.3.1 Sequencer .................................................................................................... 2-6
2.3.2 CRT Controller ............................................................................................. 2-7
2.3.3 Graphics Controller ...................................................................................... 2-8
2.3.4 Attribute Controller ..................................................................................... 2-10
2.3.5 Dual-Frequency Synthesizer ...................................................................... 2-11
2.3.6 Palette DAC ................................................................................................ 2-12
2.4 Hardware/Software Compatibility .......................................................................... 2-13
2.5 Video Subsystem Architecture .............................................................................. 2-13
3. DATA BOOK ........................................................................................... 3-3
Contents .................................................................................................................. 3-6
Conventions ............................................................................................................ 3-9
1. Pin Information ...................................................................................................... 3-11
1.1 Pin Diagram (ISA Bus) .......................................................................................... 3-11
1.2 Pin Diagram (MicroChannel® Bus) ........................................................................ 3-12
1.3 Pin Diagram (Local Bus) ....................................................................................... 3-13
1.4 Pin Summary ......................................................................................................... 3-15
2. Detailed Pin Descriptions ...................................................................................... 3-23
2.1 Host Interface — ISA Bus Mode ........................................................................... 3-23
2.2 Host Interface — MicroChannel® Bus Mode ......................................................... 3-27
2.3 Host Interface — Local Bus (CL-GD5424/’25/’26/’28/’29 only) ............................. 3-30
2.4 Dual-Frequency Synthesizer Interface .................................................................. 3-33
2.5 Video Interface ...................................................................................................... 3-34
2.6 Display Memory Interface ...................................................................................... 3-36
2.7 Miscellaneous Pins ................................................................................................ 3-37
2.8 Power Pins ............................................................................................................ 3-38
Copyright 1995 — Cirrus Logic Inc.
v
September 1997

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CONTENTS
True Color Family Technical Reference Manual
3. DATA BOOK (cont.)
3. Functional Description ...........................................................................................3-39
3.1 General ..................................................................................................................3-39
3.2 Functional Blocks ...................................................................................................3-39
3.3 Functional Operation ..............................................................................................3-41
3.4 Performance ..........................................................................................................3-42
3.5 Compatibility ..........................................................................................................3-42
3.6 Board Testability ....................................................................................................3-42
4. CL-GD542X Configuration Tables .........................................................................3-43
4.1 Video Modes ..........................................................................................................3-43
4.2 Configuration Register, CF1 ..................................................................................3-47
4.3 Host Interface Signals ............................................................................................3-48
5. VGA Register Port Map .........................................................................................3-49
6. CL-GD542X Registers ...........................................................................................3-51
7. Electrical Specifications .........................................................................................3-57
7.1 Absolute Maximum Ratings ...................................................................................3-57
7.2 DC Specifications (Digital) .....................................................................................3-58
7.3 DC Specifications (Palette DAC) ...........................................................................3-59
7.4 DC Specifications (Frequency Synthesizer) ..........................................................3-59
7.5 DAC Characteristics ...............................................................................................3-60
7.6 List of Waveforms ..................................................................................................3-61
8. Package Dimensions ...........................................................................................3-105
9. Ordering Information Examples ...........................................................................3-106
4. EXTERNAL AND GENERAL REGISTERS ............................................ 4-2
4.1 POS 94: 102 Access Control Register (Write only) .................................................4-3
4.2 POS102: POS102 Register .....................................................................................4-4
4.3 VSSM: Sleep Address Register (CL-GD5424/’25/’26/’28/’29 only) ..........................4-5
4.4 VSSM: Adapter Sleep Address Register (Write only) ..............................................4-6
4.5 MISC: Miscellaneous Output Register .....................................................................4-7
4.6 FC: Feature Control Register ...................................................................................4-9
4.7 FEAT: Input Status Register 0 ...............................................................................4-10
4.8 STAT: Input Status Register 1 ...............................................................................4-11
4.9 Pixel Mask Register ...............................................................................................4-12
4.10 Pixel Address Register (Read Mode — Write only) ...............................................4-13
4.11 DAC State Register (Read only) ............................................................................4-14
4.12 Pixel Address Register (Write Mode) .....................................................................4-15
4.13 Pixel Data Register ................................................................................................4-16
September 1997
vi Copyright 1995 — Cirrus Logic Inc.