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CL-PS7110
Data Book
FEATURES
s Ultra low power
— Designed for applications that require long battery life
while using standard AA/AAA batteries
— Average 20 mA in normal operation (everything on)
— Average 5 mA in idle mode (clock to the CPU stopped,
everything else running)
— Average 3 µA in standby mode (realtime clock on and
everything else stopped)
s Performance matching 33-MHz Intel® ’486-based
PC
— 15 Vax-MIPS (Dhrystone®) at 18 MHz
s ARM710A microprocessor
— ARM7 CPU
— 8 Kbytes of four-way set-associative cache
— MMU with 64-entry TLB (transition look-aside buffer)
— Little endian
s DRAM controller
— Connects up to four banks of DRAM, with each bank
being 32 bits wide and up to 256 Mbytes in size
(cont.)
Functional Block Diagram
Low-Power
System-on-a-Chip
OVERVIEW
The CL-PS7110 is designed for ultra-low-power
applications such as organizers/PDAs, two-way
pagers, smart phones, and hand-held internet
browsers. The device’s core-logic functionality is
built around an ARM710A microprocessor with 8
Kbytes of four-way set-associative unified cache.
At 18.432 MHz (for 3-V operation), the CL-PS7110
delivers nearly 15 Vax-MIPS of performance (based
on Dhrystone® benchmark) — roughly the same
(cont.)
3.6864 MHz
32.786 kHz
EINT[1–3],
FIQ
BATOK, EXTPWR
PWRFL, BATCHG
PORTS A B C D — 8-BIT
PORT E — 4-BIT
KEYBOARD COLUMN
DRIVES (0–7)
BUZZER DRIVE
DC TO DC
CLK, SYNC, IN,
OUT, SMPCLK
CLK, SYNC IN,
OUT
18.432-MHz
PLL
32.768-kHz
OSCILLATOR
INTERRUPT
CONTROLLER
POWER
MANAGEMENT
GPIO
PSU
CONTROL
SYNCHRONOUS
SERIAL I/O
CODEC
INTERFACE
ARM710A
ARM7
µP CORE
8-KBYTE
CACHE
MMU
COUNTERS
(2)
RTC
INTERNAL DATA BUS
STATE
CONTROL
ROM/EXPANSION
CONTROL
DRAM
CONTROLLER
INTERNAL
ADDRESS BUS
MUX
D0–D31
POR, RUN,
RESET,
WAKEUP
EXPCLK, WORD,
CD[0–7], EXPRDY,
WRITE
MOE, MWE
RAS[0–3], CAS[0–3]
A[0–27],
DRA[0–12]
LCD
CONTROLLER
LCD DRIVE
UART
IRDA
LED AND PHOTO-
DIODE
RS232 INTERFACE
Version 1.5
May 1997

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CL-PS7110
Low-Power System-on-a-Chip
FEATURES (cont.)
s ROM/SRAM/flash memory control
— Decodes eight separate memory segments of 256
Mbytes
— Each segment can be configured as 8, 16, or 32 bits
wide and support page-mode access
— Programmable access time for conventional
SRAM/ROM/flash memory
— Expansion device can also be a PC Card (PCMCIA)
controller
s Codec interface
— Provides all necessary clocks and timing pulses and
performs serialization of the data stream (or vice versa)
to or from standard telephony codecs
— Data transfer at 64 kbps
s Synchronous serial interface
— Supports SPI®1 or Microwire®2-compatible interface
s 36-bit general-purpose I/O
— Four 8-bit and one 4-bit GPIO port
— Supports scanning keyboard matrix
1 SPI is a registered trademark of Motorola®.
2 Microwire is a registered trademark of National Semicon-
ductor®.
s 16C550-style UART
— Supports bit rates up to 115.2 kbps
— Contains two 16-byte FIFOs for Tx and Rx
— Supports modem control signals
s SIR (slow (9600–115.2 kbps) infrared) encoder
— IrDA (Infrared Data Association) SIR protocol encoder
can be optionally switched into Tx and Rx signals of the
UART up to 115 kbps
s DC-to-DC converter interface
— Provides two 96-kHz clock outputs, whose duty ratio are
programmable (from 1-in-16 to 15-in-16)
s LCD controller
— Interfaces directly to a single-scan panel monochrome
LCD
— Panel size is programmable and is any width (line length)
from 16 to 1024 pixels in 16-pixel increments
— Video frame size programmable up to 128 Kbytes
— Bits per pixel programmable from 1, 2, or 4
— Two 32-bit palette registers to support 4-, 2-, or 1-bit pixel
values for mapping to any of the 16 grayscale values
s Two timer counters
s Realtime clock (32-bit)
OVERVIEW (cont.)
level of performance offered by a 33-MHz Intel® ’486-
based PC.
system. The system can have an 8-bit-wide boot
option to optimize memory size.
As shown in the system block diagram, simply adding
desired memory and peripherals to the highly inte-
grated CL-PS7110 completes a hand-held orga-
nizer/PDA system board. All the interface logic is
integrated on-chip.
The CL-PS7110 is packaged in a 208-pin VQFP
package, with a body size of 28-mm square, lead
pitch of 0.5 mm, and thickness of 1.4 mm.
Memory Interface
There are two main external memory interfaces and
a DMA controller that fetches video display data for
the LCD controller from main DRAM memory.
The SRAM/ROM-style interface has programmable
wait state timings and includes burst-mode capability,
with eight chip selects decoding eight 256-Mbyte
sections of addressable space. For maximum flexibil-
ity, each bank can be specified to be 8, 16 or 32 bits
wide to enable the use of low-cost memory in a 32-bit
The DRAM interface allows direct connection of up
to 4 banks of DRAM, each bank containing up to
256 Mbytes. To assure the lowest possible power
consumption, the CL-PS7110 supports self-refresh
DRAMs, which are placed a low-power state by the
device when it enters its low-power standby mode.
Serial Interface
For RS232 serial communications, the CL-PS7110
includes a UART with two 16-byte FIFOs for receive
and transmit data. The UART supports bit rates of
up to 115.2 kbps. An IrDA SIR protocol
encoder/decoder can be optionally switched into the
Rx/Tx signals to/from the UART to enable these sig-
nals to drive an infrared communication interface
directly.
A full-duplex codec interface allows direct connec-
tion of a standard codec chip to the CL-PS7110,
allowing storage and playback of sound.
2 May 1997
DATA BOOK v1.5

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CL-PS7110
Low-Power System-on-a-Chip
A CL-PS7110–Based System
PCMCIA
SOCKET
PCMCIA
BUFFERS
× 16
DRAM
× 16
DRAM
× 16
DRAM
× 16
DRAM
× 16
DRAM
× 16
DRAM
× 16
DRAM
× 16
DRAM
× 16
FLASH
× 16
FLASH
× 16
ROM
× 16
ROM
EXTERNAL MEMORY
MAPPED EXPANSION
BUFFERS
ADDITIONAL I/O
BUFFERS
AND
LATCHES
CL-PS7110
WRITE
CS[4]
CS[5]
EXPRDY
EXPCLK
WORD
DD[3:0]
CL1
CL2
FM
M
D[31:0]
A[27:0]
NMOE
NMWE
NRAS[3]
NRAS[2]
NRAS[1]
NRAS[0]
NCAS[0]
NCAS[1]
NCAS[2]
NCAS[3]
NCS[0]
NCS[1]
COL[7:0]
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
PE[3:0]
NPOR
NPWRFL
BATOK
NEXTPWR
NBATCHG
RUN
WAKEUP
DRIVE[1:0]
FB[1:0]
CS[6]
CS[7]
ADCCLK
NADCCS
ADCOUT
ADCIN
SMPCLK
LEDDRV
PHDIN
NCS[2]
NCS[3]
RXD
TXD
DSR
CTS
DCD
PCMCK
PCMSYNC
PCMOUT
PCMIN
LCD MODULE
KEYBOARD
POWER
SUPPLY UNIT
AND
COMPARATORS
DC
INPUT
BATTERY
DC-TO-DC
CONVERTERS
ADC
DIGITIZER
IR LED AND
PHOTODIODE
RS232
TRANSEIVER
CODEC
A separate synchronous serial interface sup-
ports two industry-standard protocols (SPI®
and Microwire®) for interfacing to standard
devices such as an ADC, allowing for peripheral
expansion such as the use of a digitizer pen.
Power Management
The CL-PS7110 is designed for low-power
operation. There are three basic power states:
q Standby — This state is equivalent to the com-
puter being switched off (no display), and the
main oscillator is shut down. Only the realtime
clock is running.
q Idle — In this state, the device is functioning and
all oscillators are running, but the processor
clock is halted while waiting for an event such as
a key press.
q Operating — This state is the same as the idle
state, except that the processor clock is running.
May 1997
DATA BOOK v1.5
3

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CL-PS7110
Low-Power System-on-a-Chip
TABLE OF CONTENTS
LIST OF TABLES.............................................................................................. 7
LIST OF FIGURES............................................................................................ 8
CONVENTIONS ................................................................................................ 9
1. FUNCTIONAL DESCRIPTION ....................................................................... 11
1.1 Overview .............................................................................................................................. 11
1.2 General ................................................................................................................................ 12
1.2.1 Clocking............................................................................................................................ 13
1.2.2 CPU Core ......................................................................................................................... 13
1.2.3 Interrupt Controller............................................................................................................ 13
1.2.4 Memory Interface and DMA.............................................................................................. 14
1.2.5 Expansion and Memory Controller for SRAM/ROM/Flash Interface................................. 17
1.2.6 DRAM Controller .............................................................................................................. 19
1.2.7 PCMCIA Support.............................................................................................................. 19
1.2.8 Codec Interface ................................................................................................................ 21
1.2.9 Synchronous Serial Interface ........................................................................................... 21
1.2.10 LCD Controller.................................................................................................................. 21
1.2.11 Internal UART and SIR Encoder....................................................................................... 22
1.2.12 Timer Counters................................................................................................................. 23
1.2.13 Realtime Clock ................................................................................................................. 23
1.2.14 DC-to-DC Converter ......................................................................................................... 23
1.2.15 Keyboard Control.............................................................................................................. 26
1.2.16 GPIO................................................................................................................................. 26
1.2.17 Buzzer Control.................................................................................................................. 26
1.2.18 Battery Management ........................................................................................................ 27
1.2.19 State Control..................................................................................................................... 27
1.2.20 Power Management.......................................................................................................... 28
1.2.21 Software Model for Power Management........................................................................... 29
1.2.22 Resets .............................................................................................................................. 29
2. PIN INFORMATION ........................................................................................ 31
2.1 Pin Diagram ......................................................................................................................... 31
2.2 Pin Description Conventions................................................................................................ 32
2.3 Pin Descriptions................................................................................................................... 32
2.4 Pin Descriptions................................................................................................................... 35
3. PROGRAMMING INTERFACE....................................................................... 39
3.1 Memory Map........................................................................................................................ 39
3.2 Internal Registers................................................................................................................. 40
3.2.1 PADR — Port A Data Register ......................................................................................... 41
3.2.2 PBDR — Port B Data Register ......................................................................................... 41
3.2.3 PCDR — Port C Data Register......................................................................................... 42
3.2.4 PDDR — Port D Data Register......................................................................................... 42
3.2.5 PADDR — Port A Data Direction Register........................................................................ 42
3.2.6 PBDDR — Port B Data Direction Register ....................................................................... 42
3.2.7 PCDDR — Port C Data Direction Register....................................................................... 42
3.2.8 PDDDR — Port D Data Direction Register....................................................................... 42
4
TABLE OF CONTENTS
May 1997
DATA BOOK v1.5

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CL-PS7110
Low-Power System-on-a-Chip
3.2.9 PEDR — Port E Data Register ......................................................................................... 42
3.2.10 PEDDR — Port E Data Direction Register ....................................................................... 42
3.2.11 SYSCON — System Control Register.............................................................................. 43
3.2.12 SYSFLG — System Status Flags Register ...................................................................... 45
3.2.13 MEMCFG1 — Memory Configuration Register 1 ............................................................. 47
3.2.14 MEMCFG2 — Memory Configuration Register 2 ............................................................. 47
3.2.15 DRFPR — DRAM Refresh Period Register...................................................................... 49
3.2.16 INTSR — Interrupt Status Register .................................................................................. 50
3.2.17 INTMR — Interrupt Mask Register ................................................................................... 52
3.2.18 LCDCON — LCD Control Register................................................................................... 52
3.2.19 TC1D — Timer Counter 1 Data Register.......................................................................... 53
3.2.20 TC2D — Timer Counter 2 Data Register.......................................................................... 53
3.2.21 RTCDR — Realtime Clock Data Register ........................................................................ 53
3.2.22 RTCMR — Realtime Clock Match Register...................................................................... 53
3.2.23 PMPCON — Pump Control Register................................................................................ 54
3.2.24 CODR — Codec Interface Data Register ......................................................................... 54
3.2.25 UARTDR — UART Data Register..................................................................................... 55
3.2.26 UBRLCR — UART Bit Rate and Line Control Register .................................................... 55
3.2.27 PALLSW Least-Significant Word-LCD Palette Register.................................................... 56
3.2.28 PALMSW Most-Significant Word-LCD Palette Register.................................................... 57
3.2.29 SYNCIO Synchronous Serial Interface Data Register...................................................... 58
3.2.30 STFCLR — Clear All Start Up Reason Flags Location .................................................... 58
3.2.31 BLEOI — Battery Low End of Interrupt............................................................................. 58
3.2.32 MCEOI — Media Changed End of Interrupt ..................................................................... 59
3.2.33 TEOI — Tick End of Interrupt Location............................................................................. 59
3.2.34 TC1EOI TC1 — End of Interrupt Location ........................................................................ 59
3.2.35 TC2EOI TC2 — End Of Interrupt Location ....................................................................... 59
3.2.36 RTCEOI — RTC Match End Of Interrupt.......................................................................... 59
3.2.37 UMSEOI — UART Modem Status Changed End of Interrupt........................................... 59
3.2.38 COEOI — Codec End of Interrupt Location...................................................................... 59
3.2.39 HALT — Enter Idle State Location.................................................................................... 59
3.2.40 STDBY — Enter Standby State Location ......................................................................... 59
4. ELECTRICAL SPECIFICATIONS .................................................................. 60
4.1 Absolute Maximum Ratings ................................................................................................. 60
4.2 Recommended Operating Conditions.................................................................................. 60
4.3 DC Characteristics............................................................................................................... 61
4.4 AC Characteristics ............................................................................................................... 62
4.5 I/O Buffer Characteristics..................................................................................................... 70
4.6 Test Modes........................................................................................................................... 70
4.6.1 Oscillator and PLL Bypass Mode ..................................................................................... 71
4.6.2 Functional (EPB) Test Mode ............................................................................................. 71
4.6.3 Oscillator and PLL Test Mode........................................................................................... 71
4.6.4 Pin Test Mode ................................................................................................................... 72
4.6.5 High-Z (System) Test Mode .............................................................................................. 73
4.6.6 Test ROM Mode................................................................................................................ 73
4.6.7 Software-Selectable Test Functionality ............................................................................. 74
5. PACKAGE SPECIFICATIONS........................................................................ 75
5.1 208-Pin VQFP Package Outline Drawing............................................................................. 75
May 1997
DATA BOOK v1.5
TABLE OF CONTENTS
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