ISL6596.pdf 데이터시트 (총 13 페이지) - 파일 다운로드 ISL6596 데이타시트 다운로드

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ISL6596
Synchronous Rectified MOSFET Driver
The ISL6596 is a high frequency, MOSFET driver optimized to
drive two N-Channel power MOSFETs in a synchronous buck
converter topology. Combine this driver with the Renesas
Multi-Phase Buck PWM controllers to form a complete
single-stage core-voltage regulator solution with high
efficiency performance at high switching frequency for
advanced microprocessors.
The IC is biased by a single low voltage supply (5V), minimizing
driver switching losses in high MOSFET gate capacitance and
high switching frequency applications. Each driver can drive a
3nF load with less than 10ns rise/fall time. Bootstrapping of
the upper gate driver is implemented with an internal low
forward drop diode, reducing implementation cost, complexity,
and allowing the use of higher performance, cost effective
N-Channel MOSFETs. Adaptive shoot-through protection is
integrated to prevent both MOSFETs from conducting
simultaneously.
The ISL6596 features 4A typical sink current for the lower gate
driver, enhancing the lower MOSFET gate hold-down capability
during the PHASE node rising edge and preventing power loss
caused by the self turn-on of the lower MOSFET due to the high
dV/dt of the switching node.
The ISL6596 also features an input that recognizes a
high-impedance state, working with Renesas multi-phase 3.3V
or 5V PWM controllers to prevent negative transients on the
controlled output voltage when operation is suspended. This
feature eliminates the need for the Schottky diode that may be
used in a power system to protect the load from negative
output voltage damage.
Applications
• Core voltage supplies for Intel® and AMD® microprocessors
• High frequency low profile high efficiency DC/DC converters
• High current low voltage DC/DC converters
• Synchronous rectification for isolated power supplies
Related Literature
For a full list of related documents, visit our website
ISL6596 product page
DATASHEET
FN9240
Rev.3.00
May 30, 2018
Features
• Drives two N-Channel MOSFETs
• Adaptive shoot-through protection
• 0.4Ω on-resistance and 4A sink current capability
• Supports high switching frequency
• Fast output rise and fall time
• Low tri-state hold-off time (20ns)
• Supports 3.3V and 5V PWM inputs
• Low quiescent supply current
• Power-On reset
• Expandable bottom copper pad for heat spreading
• Dual Flat No-Lead (DFN) package
- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat No
Leads - product outline
- Near chip-scale package footprint improves PCB
efficiency and is thinner in profile
• Pb-Free (RoHS compliant)
FN9240 Rev.3.00
May 30, 2018
Page 1 of 13

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ISL6596
Typical Application
+3.3V
PGOOD
VID
(OPTIONAL)
+3.3V
FB COMP
VCC
VSEN
PWM1
PWM2
PWM
CONTROLLER
(ISL69XX)
ISEN1
ISEN2
FS/EN
GND
+5V
VCC
BOOT
VCTRL
PWM
UGATE
ISL6596
PHASE
LGATE
+5V
VCC
BOOT
VCTRL
PWM
UGATE
ISL6596
PHASE
LGATE
VIN
RUGPH
VIN
RUGPH
+VCORE
RUGPH IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS
FIGURE 1. MULTI-PHASE CONVERTER USING ISL6596 GATE DRIVERS (SEE “APPLICATION INFORMATION” ON PAGE 9)
Block Diagram
VCC
VCTRL
PWM
7k
CONTROL
LOGIC
7k
SHOOT-
THROUGH
PROTECTION
VCC
VCTRL = CONTROLLER VCC
FIGURE 2. BLOCK DIAGRAM
BOOT
UGATE
PHASE
LGATE
GND
FN9240 Rev.3.00
May 30, 2018
Page 2 of 13

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ISL6596
Ordering Information
PART NUMBER
(Notes 2, 3)
PART MARKING
TEMP RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
(RoHS COMPLIANT)
PKG. DWG. #
ISL6596CBZ
6596 CBZ
(No longer available, recommended
replacement: ISL6596CRZ)
0 to +70
- 8 Ld SOIC
M8.15
ISL6596CRZ
596Z
0 to +70
-
10 Ld 3x3 DFN
L10.3x3C
ISL6596CRZ-T
596Z
0 to +70
6k 10 Ld 3x3 DFN L10.3x3C
ISL6596IBZ (No longer available,
recommended replacement:
ISL6596IRZ)
6596 IBZ
-40 to +85
- 8 Ld SOIC
M8.15
ISL6596IRZ
96IZ
-40 to +85
-
10 Ld 3x3 DFN
L10.3x3C
ISL6596IRZ-T
96IZ
-40 to +85
6k 10 Ld 3x3 DFN L10.3x3C
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), refer to the ISL6596 product information page. For more information about MSL, see TB363.
Pinouts
8 LD SOIC
TOP VIEW
UGATE 1
BOOT 2
PWM 3
NGONLDONG4ER
AVAILABLE
OR
SUP87PORPVTCHETADRSLE
6 VCC
5 LGATE
10 LD DFN
TOP VIEW
UGATE 1
BOOT 2
N/C 3
PWM 4
GND 5
10 PHASE
9 VCTRL
8 N/C
7 VCC
6 LGATE
Functional Pin Descriptions
PIN NUMBER (Note 4)
1
2
3, 8
4
5
6
7
PIN NAME
UGATE
BOOT
N/C
PWM
GND
LGATE
VCC
DESCRIPTION
Upper gate drive output. Connect to the gate of the high-side N-Channel power MOSFET. A gate resistor
is never recommended on this pin because it interferes with the operation shoot-through protection
circuitry.
Floating bootstrap supply pin for the upper gate drive. Connect a bootstrap capacitor between this pin
and the PHASE pin. The bootstrap capacitor provides the charge used to turn on the upper MOSFET.
See “Bootstrap Considerations” on page 7 for information about choosing the appropriate capacitor
value.
Do not connect.
Driver control input. The PWM signal can enter three distinct states during operation. See “PWM Input and
Threshold Control” on page 7 for more information. Connect this pin to the controller PWM output.
Ground pin. All signals are referenced to this node.
Lower gate drive output. Connect to the gate of the low side N-Channel power MOSFET. A gate resistor
is never recommended on this pin because it interferes with the operation shoot-through protection
circuitry.
Connect this pin to a +5V bias supply. Bypass locally to ground with a high quality ceramic capacitor.
FN9240 Rev.3.00
May 30, 2018
Page 3 of 13

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ISL6596
Functional Pin Descriptions
PIN NUMBER (Note 4)
PIN NAME
DESCRIPTION
9
VCTRL
Sets the PWM logic threshold. Connect this pin to a 3.3V source for 3.3V PWM input and pull it to a 5V
source for 5V PWM input.
10
PHASE
Provides the return path for the upper gate driver current. Connect this pin to the upper MOSFET
source.
- Thermal Pad (DFN The metal pad underneath the center of the IC is a thermal substrate. The PCB “thermal land” design
package only)
for this exposed die pad should include vias that drop down and connect to one or more buried
copper plane(s). This combination of vias for vertical heat escape and buried planes for heat
spreading allows the DFN to achieve its full thermal potential. This pad should be either grounded
or floating, and it should not be connected to other nodes. Refer to TB389 for design guidelines.
NOTES:
4. Pin numbers refer to the DFN package. Refer to “Pinouts” on page 3 for the corresponding SOIC pinout.
FN9240 Rev.3.00
May 30, 2018
Page 4 of 13

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ISL6596
Absolute Maximum Ratings
Supply Voltage (VCC, VCTRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Input Voltage (VEN, VPWM) . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . -0.3V to 33V (DC) or 36V (<200ns)
BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . . . . . . . . . . -0.3V to 7V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to 30V (DC)
. . . . . . . . . . . . . . .GND - 8V (<20ns Pulse-Width, 10µJ) to 30V (<100ns)
UGATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
. . . . . . . . . . . . . . . . . . .VPHASE - 5V (<20ns Pulse-Width, 10µJ) to VBOOT
LGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
. . . . . . . . . . . . . . . . . GND - 2.5V (<20ns Pulse-Width, 5µJ) to VCC + 0.3V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
HBM ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
SOIC Package (Note 5) . . . . . . . . . . . . . . . 110
N/A
DFN Package (Notes 6, 7) . . . . . . . . . . . . 48
7
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
6. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379
for details.
7. For JC, the “case temp” location is at the center of the package underside exposed pad.
Electrical Specifications These specifications apply to the limits in “Absolute Maximum Ratings”, unless otherwise noted.
PARAMETER
VCC SUPPLY CURRENT
Bias Supply Current
POR Rising
POR Falling
Hysteresis
VCTRL INPUT
Rising Threshold
Falling Threshold
PWM INPUT
Sinking Impedance
Source Impedance
Tri-State LowerThreshold
Tri-State Upper Threshold
Tri-State Shutdown Holdoff Time
SWITCHING TIME (See Figure 3 on page 6 )
UGATE Rise Time (Note 8)
LGATE Rise Time (Note 8)
UGATE Fall Time (Note 8)
LGATE Fall Time (Note 8)
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
SYMBOL
TEST CONDITIONS
IVCC PWM pin floating, VVCC = 5V
RPWM_SNK
RPWM_SRC
tTSSHD
VVCTRL = 3.3V (-110mV Hysteresis)
VVCTRL = 5V (-250mV Hysteresis)
VVCTRL = 3.3V (+110mV Hysteresis)
VVCTRL = 5V (+250mV Hysteresis)
tPDLU or tPDLL + Gate Falling Time
tRU
tRL
tFU
tFL
tPDLU
tPDLL
tPDHU
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, 3nF Load
VVCC = 5V, Outputs Unloaded
VVCC = 5V, Outputs Unloaded
VVCC = 5V, Outputs Unloaded
MIN MAX
(Note 9) TYP (Note 9) UNIT
- 190 -
- 3.4 4.2
2.2 3.0
-
- 400 -
µA
V
V
mV
- 2.75 2.90
2.4 2.65
-
V
V
- 3.5 -
- 3.5 -
- 1.1 -
- 1.5 -
- 1.9 -
- 3.25 -
- 20 -
kΩ
kΩ
V
V
V
V
ns
- 8.0 -
- 8.0 -
- 8.0 -
- 4.0 -
- 20 -
- 15 -
- 19 -
ns
ns
ns
ns
ns
ns
ns
FN9240 Rev.3.00
May 30, 2018
Page 5 of 13