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DATASHEET
ISL6260, ISL6260B
Multiphase Core Regulator for IMVP-6 Mobile CPUs
FN9162
Rev 1.00
Jan 3, 2006
The ISL6260 and ISL6260B provide microprocessor core
voltage regulation by driving up to 3 channels in parallel. The
multiphase buck converter architecture uses interleaved
channels to multiply the output voltage ripple frequency and
reduce output channel currents. The reduction in ripple results
in fewer components, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL6260,
ISL6260B multiphase controller together with the ISL6208 gate
drivers form the basis for a portable power supply solution to
power Intel's next generation mobile microprocessors. The
modulator at the heart of this power system is derived from
Intersil's Robust Ripple Regulator technology, (R3) Compared
with the traditional multiphase buck regulator, the R3
technology multiphase converter has faster transient response.
This is due to the R3 modulator commanding variable switching
frequency during load transients.
Intel Mobile Voltage Positioning is a smart voltage regulation
technology, which effectively reduces power dissipation in Intel
Pentium processors. The ISL6260 and ISL6260B support the
IMVP-6 mobile processor voltage regulation specifications.
ISL6260 and ISL6260B are pin-to-pin compatible. ISL6260B
responds to PSI# signal by adding or dropping PWM2 and
adjusting overcurrent protection accordingly. To improve
audible noise, the DPRSLPVR signal can be used to reduce
slew rates entering and exiting Deeper Sleep.
The ISL6260 and ISL6260B have several other key features.
Current sensing can be done using either DCR sensing or
discrete precision resistor sensing. A single NTC thermistor
thermally compensates both the gain and time constant of
the DCR variation. A unity gain, differential amplifier is
provided for remote CPU die sensing. This allows the
voltage on the CPU die to be accurately measured and
regulated per Intel IMVP-6 specifications.
Ordering Information
PART NUMBER PART
(Note)
MARKING
TEMP.
RANGE
(°C)
PACKAGE PKG.
(Pb-FREE) DWG. #
ISL6260CRZ ISL6260CRZ -10 to 100 40 Ld 6x6 QFN L40.6x6
ISL6260CRZ-T ISL6260CRZ -10 to 100 40 Ld 6x6 QFN L40.6x6
ISL6260BCRZ ISL6260BCRZ -10 to 100 40 Ld 6x6 QFN L40.6x6
ISL6260BCRZ-T ISL6260BCRZ -10 to 100 40 Ld 6x6 QFN L40.6x6
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Multiple Current Sensing Approaches Supported
- Lossless DCR Current Sensing
- Precision Resistive Current Sensing
• Supports PSI# and Narrow VDC for Enhanced Battery Life
(EBL) Initiatives
• Superior Noise Immunity and Transient Response
• Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1, 2 or 3 Power Channels
• Balanced Channel Loading Including Transients
• Small Footprint QFN 40 Lead 6x6 Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Mobile laptop computers
Pinout
ISL6260CRZ, ISL6260BCRZ (QFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
PSI# 1
PGD_IN 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
GND PAD
(BOTTOM)
30 VID2
29 VID1
28 VID0
27 PWM1
26 PWM2
25 PWM3
24 FCCM
23 ISEN1
22 ISEN2
21 ISEN3
11 12 13 14 15 16 17 18 19 20
FN9162 Rev 1.00
Jan 3, 2006
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ISL6260, ISL6260B
Functional Pin Description
40 39 38 37 36 35 34 33 32 31
PSI# 1
PGD_IN 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
GND PAD
(BOTTOM)
30 VID2
29 VID1
28 VID0
27 PWM1
26 PWM2
25 PWM3
24 FCCM
23 ISEN1
22 ISEN2
21 ISEN3
11 12 13 14 15 16 17 18 19 20
PSI#
Low load current indicator input. When asserted low,
indicates a reduced load-current condition. For ISL6260B,
when PSI# is asserted low, PWM2 will be disabled.
PGD_IN
Digital Input. When asserted high, indicates VCCP and
VCC_MCH voltages are within regulation. PGD_IN signal
high is needed for the CLK_EN# to be low and PGOOD to
be high.
RBIAS
147K Resistor to VSS sets internal current reference.
VR_TT#
Thermal overload output indicator.
NTC
Thermistor input to VRTT# circuit.
SOFT
A capacitor from this pin to Vss sets the maximum slew rate
of the output voltage. Soft pin is the non-inverting input of the
error amplifier.
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
VW
A resistor from this pin to COMP programs the switching
frequency. (7kgives approximately 300kHz). VW pin
sources current.
COMP
This pin is the output of the error amplifier.
FB
This pin is the inverting input of error amplifier.
VDIFF
This pin is the output of the differential amplifier.
VSEN
Remote core voltage sense input. Connect to micro-
processor die.
RTN
Remote voltage sensing return. Connect to ground at micro-
processor die.
DROOP
Output of droop amplifier. Output = VO + DROOP.
DFB
Inverting input to droop amplifier.
VO
An input to the IC that reports the local output voltage.
VSUM
This pin is connected to the current summation junction.
VIN
Battery supply voltage, used for feed forward.
VSS
Signal ground; Connect to local controller ground.
VDD
5V bias power.
ISEN3
Individual current sensing for channel 3.
ISEN2
Individual current sensing for channel 2.
ISEN1
Individual current sensing for channel 1.
FCCM
Forced Continuous Conduction Mode (FCCM) enable pin to
MOSFET drivers. It will disable diode emulation.
PWM3
PWM output for channel 3.
FN9162 Rev 1.00
Jan 3, 2006
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ISL6260, ISL6260B
PWM2
PWM output for channel 2. For ISL6260B, PSI# low will
make this output tri-state.
PWM1
PWM output for channel 1.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB.
CLK_EN#
Digital output to enable System PLL Clock; Goes active
10µs after PG_IN is active and Vcore is within 10% of Boot
Voltage.
PGOOD
Power Good open-drain output. Will be pulled up externally
by a 680resistor to VCCP or 1.9kto 3.3V.
3V3
3.3V supply voltage for CLK_EN# logic, such an
implementation will improve power consumption from 3.3V
compared to open drain circuit other wise.
VR_ON
Voltage Regulator enable input. A high level logic signal on
this pin enables the regulator.
DPRSLPVR
Deeper Sleep Enable signal. A high level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode and indicates that slow entry and exit from C4 should
occur. DPRSLPVR low indicates large charging or
discharging soft pin current, and therefore fast output
voltage transitions.
DPRSTP#
Deeper Sleep Enable signal. A low level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode.
FN9162 Rev 1.00
Jan 3, 2006
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ISL6260, ISL6260B
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . -0.3 - +7V
ALL OTHER PINS . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 100°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . +5V ±5%
Thermal Information
Thermal Resistance
JA (°C/W) JC (°C/W)
QFN Package (Notes 1, 2) . . . . . . . . .
30
5.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . +300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, unless otherwise noted.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
2.9
+3.3V Supply Current
Battery Supply Current
VIN Input Resistance
Power-On-Reset Threshold
SYSTEM AND REFERENCES
I3V3
IVIN
RVIN
PORr
PORf
No load on CLK_EN#
VR_ON = 0V
VR_ON = 3.3V
VDD rising
VDD falling
900
4.35
4.00 4.15
System Accuracy
%Error
(VCC_CORE)
No load; closed loop, active mode range
VID = 0.75V - 1.50V
VID = 0.5V - 0.7375V
-0.5
-8
VID = 0.3 - 0.4875V
-15
VBOOT
Maximum Output Voltage
Minimum Output Voltage
VID Off State
VCC_CORE(max) VID = [0000000]
VCC_CORE(min) VID = [1100000]
VID = [1111111]
1.176
1.200
1.500
0.300
0.0
RBIAS Voltage
CHANNEL FREQUENCY
RBIAS = 147k
1.45 1.47
Nominal Channel Frequency
Adjustment Range
fSW(nom)
Rfset = 7k, 3 channel operation, Vcomp = 2V
See Equation 4 Rfset selection
285
200
300
AMPLIFIERS
Droop Amplifier Offset
-0.3
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
FB Input Current
Av0
GBW
IIN(FB)
CL= 20pF
90
18
10
MAX UNITS
3.5 mA
1 µA
1 µA
1 µA
k
4.5 V
V
+0.5
%
+8
+15
1.224
1.49
mV
mV
V
V
V
V
V
315 kHz
500 kHz
+0.3
150
mV
dB
MHz
nA
FN9162 Rev 1.00
Jan 3, 2006
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ISL6260, ISL6260B
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C, unless otherwise noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
ISEN
Imbalance Voltage
Maximum of ISENs - Minimum of ISENs
2
Input Bias Current
20
SOFT CURRENT
Soft-start current
ISS
SOFT Geyserville Current
IGV
SOFT Deeper Sleep Entry Current
IC4
SOFT Deeper Sleep Exit Current
IC4EA
SOFT Deeper Sleep Exit Current
IC4EB
POWER GOOD AND PROTECTION MONITORS
|SOFT-VDAC| >100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-46
175
-46
36
175
-41
200
-41
41
200
-36
225
-36
46
225
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
VOL
IOH
tpgd
IPGOOD= 4mA
PGOOD = 3.3V
CLK_ENABLE# LOW to PGOOD HIGH
0.26 0.4
-1 1
5.5 6.8 8.1
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OVH
OVHS
VO rising above setpoint for >1ms
VO rising for >2µs
I(Rbias) = 10µA
160 200 240
1.675 1.7 1.725
9.8 10 10.2
OC Threshold Offset
DROOP rising above OCSET for >150s
-2
4
Current Imbalance Threshold
One ISEN above another ISEN for >1.2ms
9
Undervoltage Threshold
(VDIFF/SOFT)
UVf VO falling below setpoint for >1.2ms
-355
-295
-235
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL(3.3V)
1.0
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH(3.3V)
2.3
VID0-VID6, PSI#, DPRSTP# Input
Low
VIL(1.0V)
0.3
VID0-VID6, PSI#, DPRSTP# Input
High
VIH(1.0V)
0.7
PWM
PWM (PWM1-PWM3) Output Low
FCCM Output Low
VOL(5.0V)
VOL_FCCM
Sinking 5mA
Sinking 3mA
1.0
1.0
PWM (PWM1-PWM3) and FCCM
Output High
VOH(5.0V) Sourcing 5mA
3.5
PWM Tri-State Leakage
PWM = 2.5V
-1 1
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
53 60 67
Over-Temperature Threshold
V (NTC) falling
1.165 1.18
1.2
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
RTT I = 20mA
6.5 9
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
VOH
VOL
3V3 = 3.3V, I = -4mA
I = 4mA
2.9 3.1
0.26 0.4
UNITS
mV
nA
A
A
A
A
A
V
A
ms
mV
V
A
mV
mV
mV
V
V
V
V
V
V
V
A
A
V
V
V
FN9162 Rev 1.00
Jan 3, 2006
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