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512Mb, 3V Multiple I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 64KB, Sector Erase
MT25QL512AB
Features
• SPI-compatible serial bus interface
• Single and double transfer rate (STR/DTR)
• Clock frequency
– 133 MHz (MAX) for all protocols in STR
– 66 MHz (MAX) for all protocols in DTR
• Dual/quad I/O commands for increased through-
put up to 65 MB/s
• Supported protocols in both STR and DTR
– Extended I/O protocol
– Dual I/O protocol
– Quad I/O protocol
• Execute-in-place (XIP)
• PROGRAM/ERASE SUSPEND operations
• Volatile and nonvolatile configuration settings
• Software reset
• Additional reset pin for selected part numbers
• 3-byte and 4-byte address modes – enable memory
access beyond 128Mb
• Dedicated 64-byte OTP area outside main memory
– Readable and user-lockable
– Permanent lock with PROGRAM OTP command
• Erase capability
– Bulk erase
– Sector erase 64KB uniform granularity
– Subsector erase 4KB, 32KB granularity
• Security and write protection
– Volatile and nonvolatile locking and software
write protection for each 64KB sector
– Nonvolatile configuration locking
– Password protection
– Hardware write protection: nonvolatile bits
(BP[3:0] and TB) define protected area size
– Program/erase protection during power-up
– CRC detects accidental changes to raw data
• Electronic signature
– JEDEC-standard 3-byte signature (BA20h)
– Extended device ID: two additional bytes identify
device factory options
• JESD47H-compliant
– Minimum 100,000 ERASE cycles per sector
– Data retention: 20 years (TYP)
Options
• Voltage
– 2.7–3.6V
• Density
– 512Mb
• Device stacking
– Monolithic
• Lithography
– 45nm
• Die revision
• Pin configuration
– RESET and HOLD#
• Production status
– Engineering samples
• Operating temperature range
– From –40°C to +85°C
– From –40°C to +105°C
• Special options
– Standard
– Automotive
• Standard security
• Packages – JEDEC-standard, RoHS-
compliant
– 16-pin SOP2, 300 mils
(SO16W, SO16-Wide, SOIC-16)
– 24-ball T-PBGA 05/6mm x 8mm
(TBGA24)
• Sector Size
– 64KB
Marking
L
512
A
B
A
8
ES
IT
AT
S
A
0
SF
12
E
PDF: 09005aef84fe19ac
qlks_512mb_3V_45nm.pdf - Rev. C 12/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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512Mb, 3V Multiple I/O Serial Flash Memory
Features
Part Number Ordering
Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Ordering Information
MT 25Q L xxx A BA 1 E SF - 0 S IT ES
Micron Technology
Part Family
25Q = SPI NOR
Voltage
L = 2.7–3.6V
U = 1.7–2.0V
Density
064 = 64Mb (8MB)
128 = 128Mb (16MB)
256 = 256Mb (32MB)
512 = 512Mb (64MB)
01G = 1Gb (128MB)
02G = 2Gb (256MB)
Stack
A = 1 die/1 S#
B = 2 die/1 S#
C = 4 die/1 S#
Litho
B = 45nm
Die Revision
A = Rev. A
Pin Configuration Option
1 = HOLD# pin
3 = RESET# pin
8 = RESET# & HOLD# pin
Production Status
Blank = Production
ES = Engineering samples
QS = Qualification samples
Operating Temperature
IT = –40°C to +85°C
AT = –40°C to +105°C (Grade 2 AEC-Q100)
Special Options
S = Standard
A = Automotive quality
Security Features
0 = Standard default security
Package Codes
12 = 24-ball T-PBGA, 05/6 x 8mm (5 x 5 array)
14 = 24-ball T-PBGA, 05/6 x 8mm (6 x 4 array)
SC = 8-pin SOP2, 150 mil
SE = 8-pin SOP2, 208 mil
SF = 16-pin SOP2, 300 mil
W7 = 8-pin W-PDFN, 6 x 5 mm “sawn”
W8 = 8-pin W-PDFN, 8 x 6mm “sawn”
W9 = 8-pin W-PDFN, 8 x 6mm “sawn”
Sector size
E = 64KB
PDF: 09005aef84fe19ac
qlks_512mb_3V_45nm.pdf - Rev. C 12/13 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.

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512Mb, 3V Multiple I/O Serial Flash Memory
Features
Contents
Device Description ........................................................................................................................................... 8
Device Diagram ............................................................................................................................................ 8
Advanced Security Protection ....................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Signal Descriptions ......................................................................................................................................... 10
Package Dimensions – 16-Pin SOP2 ................................................................................................................. 11
Package Dimensions – 24-Ball T-PBGA ............................................................................................................ 12
Memory Organization .................................................................................................................................... 13
Memory Map – 512Mb Density ....................................................................................................................... 14
Status Register ................................................................................................................................................ 15
Block Protection Settings ............................................................................................................................ 16
Flag Status Register ......................................................................................................................................... 17
Extended Address Register .............................................................................................................................. 18
Internal Configuration Register ....................................................................................................................... 19
Nonvolatile Configuration Register .................................................................................................................. 20
Volatile Configuration Register ........................................................................................................................ 22
Supported Clock Frequencies ..................................................................................................................... 23
Enhanced Volatile Configuration Register ........................................................................................................ 24
Security Registers ........................................................................................................................................... 25
Sector Protection Security Register .................................................................................................................. 26
Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 27
Volatile Lock Bit Security Register .................................................................................................................... 27
Device ID Data ............................................................................................................................................... 28
Serial Flash Discovery Parameter Data ............................................................................................................. 29
Command Definitions .................................................................................................................................... 33
Software RESET Operations ............................................................................................................................ 39
RESET ENABLE and RESET MEMORY Commands ....................................................................................... 39
READ ID Operations ....................................................................................................................................... 40
READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 40
READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 41
READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 41
READ MEMORY Operations ............................................................................................................................ 42
4-BYTE READ MEMORY Operations ................................................................................................................ 42
READ MEMORY Operations Timings ............................................................................................................... 43
WRITE ENABLE/DISABLE Operations ............................................................................................................. 52
READ REGISTER Operations ........................................................................................................................... 54
WRITE REGISTER Operations ......................................................................................................................... 55
CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 57
PROGRAM Operations .................................................................................................................................... 58
4-BYTE PROGRAM Operations ........................................................................................................................ 59
PROGRAM Operations Timings ....................................................................................................................... 60
ERASE Operations .......................................................................................................................................... 64
SUSPEND/RESUME Operations ..................................................................................................................... 66
PROGRAM/ERASE SUSPEND Operations .................................................................................................... 66
PROGRAM/ERASE RESUME Operations ...................................................................................................... 66
ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 68
READ OTP ARRAY Command ...................................................................................................................... 68
PROGRAM OTP ARRAY Command .............................................................................................................. 68
ADDRESS MODE Operations .......................................................................................................................... 70
ENTER QUAD and RESET QUAD Operations ................................................................................................... 70
PDF: 09005aef84fe19ac
qlks_512mb_3V_45nm.pdf - Rev. C 12/13 EN
3 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.

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512Mb, 3V Multiple I/O Serial Flash Memory
Features
ENTER QUAD or RESET QUAD Command .................................................................................................. 70
CYCLIC REDUNDANCY CHECK Operations .................................................................................................... 71
State Table ..................................................................................................................................................... 73
XIP Mode ....................................................................................................................................................... 74
Activate or Terminate XIP Using Volatile Configuration Register ................................................................... 74
Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. 74
Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. 75
Terminating XIP After a Controller and Memory Reset ................................................................................. 75
Power-Up and Power-Down ............................................................................................................................ 77
Power-Up and Power-Down Requirements .................................................................................................. 77
Power Loss and Interface Rescue ..................................................................................................................... 79
Recovery .................................................................................................................................................... 79
Power Loss Recovery ................................................................................................................................... 79
Interface Rescue ......................................................................................................................................... 79
Absolute Ratings and Operating Conditions ..................................................................................................... 80
DC Characteristics and Operating Conditions .................................................................................................. 82
AC Characteristics and Operating Conditions .................................................................................................. 83
AC Reset Specifications ................................................................................................................................... 85
Program/Erase Specifications ......................................................................................................................... 89
Revision History ............................................................................................................................................. 90
Rev. C – 012/13 ........................................................................................................................................... 90
Rev. B – 012/13 ........................................................................................................................................... 90
Rev. A – 07/13 ............................................................................................................................................. 90
PDF: 09005aef84fe19ac
qlks_512mb_3V_45nm.pdf - Rev. C 12/13 EN
4 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.

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512Mb, 3V Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Part Number Ordering Information .................................................................................................... 2
Figure 2: Logic Diagram ................................................................................................................................... 8
Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 9
Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9
Figure 5: 300mm Body Width– Package Code: SF ............................................................................................ 11
Figure 6: 5 x 5 ball grid array – 6mm x 8mm (Package Code: 12) ....................................................................... 12
Figure 7: Block Diagram ................................................................................................................................ 13
Figure 8: Memory Array Segments ................................................................................................................. 18
Figure 9: Internal Configuration Register ........................................................................................................ 19
Figure 10: Sector and Password Protection ..................................................................................................... 25
Figure 11: RESET ENABLE and RESET MEMORY Command ........................................................................... 39
Figure 12: READ ID and MULTIPLE I/O READ ID Commands ......................................................................... 40
Figure 13: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 41
Figure 14: READ – 03h/13h3 ........................................................................................................................... 43
Figure 15: FAST READ – 0Bh/0Ch3 ................................................................................................................. 43
Figure 16: DUAL OUTPUT FAST READ – 3Bh/3Ch3 ......................................................................................... 45
Figure 17: DUAL INPUT/OUTPUT FAST READ – BBh/BCh3 ............................................................................ 45
Figure 18: QUAD OUTPUT FAST READ – 6Bh/6Ch3 ........................................................................................ 46
Figure 19: QUAD INPUT/OUTPUT FAST READ – EBh/ECh3 ............................................................................ 46
Figure 20: QUAD INPUT/OUTPUT WORD READ – E7h3 ................................................................................. 47
Figure 21: DTR FAST READ – 0Dh/E0h3 .......................................................................................................... 48
Figure 22: DTR DUAL OUTPUT FAST READ – 3Dh3 ........................................................................................ 49
Figure 23: DTR DUAL INPUT/OUTPUT FAST READ – BDh3 ............................................................................ 49
Figure 24: DTR QUAD OUTPUT FAST READ – 6Dh3 ........................................................................................ 50
Figure 25: DTR QUAD INPUT/OUTPUT FAST READ – EDh3 ............................................................................ 50
Figure 26: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 53
Figure 27: READ REGISTER Timing ................................................................................................................ 54
Figure 28: WRITE REGISTER Timing .............................................................................................................. 56
Figure 29: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 57
Figure 30: PAGE PROGRAM Command .......................................................................................................... 60
Figure 31: DUAL INPUT FAST PROGRAM Command ...................................................................................... 61
Figure 32: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 61
Figure 33: QUAD INPUT FAST PROGRAM Command ..................................................................................... 62
Figure 34: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 63
Figure 35: SUBSECTOR and SECTOR ERASE Timing ....................................................................................... 65
Figure 36: BULK ERASE Timing ...................................................................................................................... 65
Figure 37: PROGRAM/ERASE SUSPEND or RESUME Timing .......................................................................... 67
Figure 38: READ OTP Command .................................................................................................................... 68
Figure 39: PROGRAM OTP Command ............................................................................................................ 69
Figure 40: XIP Mode Directly After Power-On .................................................................................................. 74
Figure 41: Power-Up Timing .......................................................................................................................... 78
Figure 42: AC Timing Input/Output Reference Levels ...................................................................................... 81
Figure 43: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 86
Figure 44: Reset Enable and Reset Memory Timing ......................................................................................... 86
Figure 45: Serial Input Timing ........................................................................................................................ 86
Figure 46: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 87
Figure 47: Hold Timing .................................................................................................................................. 88
Figure 48: Output Timing .............................................................................................................................. 88
PDF: 09005aef84fe19ac
qlks_512mb_3V_45nm.pdf - Rev. C 12/13 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.