ISL62873.pdf 데이터시트 (총 17 페이지) - 파일 다운로드 ISL62873 데이타시트 다운로드

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ISL62873
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DATASHEET
FN6930
PWM DC/DC Controller with VID Inputs for Portable GPU Core-Voltage Regulator
Rev 1.00
August 31, 2010
The ISL62873 is a Single-Phase Synchronous-Buck PWM
voltage regulator featuring Intersil’s Robust Ripple Regulator
(R3) Technology™. The wide 3.3V to 25V input voltage range
is ideal for systems that run on battery or AC-adapter power
sources. The ISL62873 is a low-cost solution for applications
requiring dynamically selected slew-rate controlled output
voltages. The soft-start and dynamic setpoint slew-rates are
capacitor programmed. Voltage identification logic-inputs
select two resistor-programmed setpoint reference voltages
that directly set the output voltage of the converter between
0.5V to 1.5V, and up to 3.3V using a feedback voltage divider.
Optionally, an external reference such as the DAC output from
a microcontroller, can be used by either IC to program the
setpoint reference voltage, and still maintain the controlled
slew-rate features. Robust integrated MOSFET drivers and
Schottky bootstrap diode reduce the implementation area and
lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The PWM
frequency is 300kHz during static operation, becoming
variable during changes in load, setpoint voltage, and input
voltage when changing between battery and AC-adapter
power. The modulators ability to change the PWM switching
frequency during these events in conjunction with external
loop compensation produces superior transient response.
For maximum efficiency, the converter automatically enters
diode-emulation mode (DEM) during light-load conditions
such as system standby.
Pinout
ISL62873
(16 LD 2.6X1.8 µTQFN)
TOP VIEW
GND 1
EN 2
VID0 3
SREF 4
12 BOOT
11 UGATE
10 PHASE
9 OCSET
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load up to 30A
• Flexible Output Voltage Programmability
- 1-Bit VID Selects Two Independent Setpoint Voltages
- Simple Resistor Programming of Setpoint Voltages
- Accepts External Setpoint Reference such as DAC
• ±0.75% System Accuracy: -10°C to +100°C
• One Capacitor Programs Soft-start and Setpoint Slew-rate
• Fixed 300kHz PWM Frequency in Continuous Conduction
• External Compensation Affords Optimum Control Loop
Tuning
• Automatic Diode Emulation Mode for Highest Efficiency
• Integrated High-current MOSFET Drivers and Schottky
Boot-Strap Diode for Optimal Efficiency
• Choice of Overcurrent Detection Schemes
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Power-Good Monitor for Soft-Start and Fault Detection
• Fault Protection
- Undervoltage
- Overcurrent (DCR-Sense or Resistive-Sense Capability)
- Over-Temperature Protection
- Fault Identification by PGOOD Pull-Down Resistance
• Pb-Free (RoHS compliant)
Applications
• Mobile PC Graphical Processing Unit VCC Rail
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Mobile PC Memory Controller Hub (GMCH) VCC Rail
• Built-In Voltage Margin for System-Level Test
FN6930 Rev 1.00
August 31, 2010
Page 1 of 17

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ISL62873
Functional Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
GND
EN
VID0
SREF
SET0
PGOOD
FB
VO
OCSET
PHASE
UGATE
BOOT
VCC
PVCC
LGATE
PGND
DESCRIPTION
IC ground for bias supply and signal reference.
Enable input for the IC. Pulling EN above the VENTHR rising threshold voltage
initializes the soft-start sequence.
Logic input for setpoint voltage selector. Use to select between the two setpoint
reference voltages. External reference input when enabled by connecting the SET0
pin to the VCC pin.
Soft-start and voltage slew-rate programming capacitor input. Setpoint reference
voltage programming resistor input. Connects internally to the inverting input of
the VSET voltage setpoint amplifier. See Figure 5 on page 9 for capacitor and
resistor connections.
Voltage set-point programming resistor input. See Figure 5 on page 9 for resistor
connection.
Power-good open-drain indicator output. This pin changes to high impedance when
the converter is able to supply regulated voltage. The pull-down resistance
between the PGOOD pin and the GND pin identifies which protective fault has shut
down the regulator. See Table 2 on page 12.
Voltage feedback sense input. Connects internally to the inverting input of the
control-loop error amplifier. The converter is in regulation when the voltage at the
FB pin equals the voltage on the SREF pin. The control loop compensation network
connects between the FB pin and the converter output. See Figure 9 on page 13.
Output voltage sense input for the R3 modulator. The VO pin also serves as the
reference input for the overcurrent detection circuit. See Figure 6 on page 10.
Input for the overcurrent detection circuit. The overcurrent setpoint programming
resistor ROCSET connects from this pin to the sense node. See Figure 6 on
page 10.
Return current path for the UGATE high-side MOSFET driver. VIN sense input for
the R3 modulator. Inductor current polarity detector input. Connect to junction of
output inductor, high-side MOSFET, and low-side MOSFET. See “Application
Schematics” on page 4 (Figures 2 and 3).
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side
MOSFET of the converter.
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is
internally connected to the cathode of the Schottky boot-strap diode. Connect an
MLCC between the BOOT pin and the PHASE pin.
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at
least a 1µF MLCC to the GND pin. See “Application Schematics” on page 4
(Figures 2 and 3).
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally
connected to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC
pin and decouple with a 10µF MLCC to the PGND pin. See“Application Schematics”
on page 4 (Figures 2 and 3).
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side
MOSFET of the converter.
Return current path for the LGATE MOSFET driver. Connect to the source of the
low-side MOSFET.
Ordering Information
PART
NUMBER
(Note)
PART MARKING
TEMP
RANGE
(°C)
PACKAGE
Tape & Reel
(Pb-Free)
PKG.
DWG. #
ISL62873HRUZ-T*
GAP
-10 to +100
16 Ld 2.6x1.8 µTQFN
L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6930 Rev 1.00
August 31, 2010
Page 2 of 17

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Block Diagram
FB
SREF
SET0
VID0
GND
EN VCC
POR
100k
EA
VCOMP
100pF
VSET
SW0
SW1
FAULT
RUN
H
L
VW IN
PWM
RUN
DRIVER
OTP
SHOOT-THROUGH
PROTECTION
PWM RUN DRIVER
gmVIN
VCC
Cr
VR
gmVO
BOOT
UGATE
PHASE
PVCC
LGATE
PGND
VID DECODER
INT
500mV
EXT
SW4
VREF
FB
UVP
FAULT
OCP
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62873
IOCSET
10µF
VO
OCSET
PGOOD

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ISL62873
Application Schematics
RVCC
+5V
CPVCC
CVCC
GPIO
GND
EN
VID0
SREF
1
2
3
4
12 BOOT
11 UGATE
PHASE
10
OCSET
9
CBOOT
QHS
QLS
VIN
3.3V TO 25V
CINC
CINB
LO
COCSET
VOUT
0.5V TO 3.3V
COC
COB
RSET1
VCC
RCOMP
CCOMP
RO
RFB
GPIO
FIGURE 2. ISL62873 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
+5V
GPIO
RVCC
CPVCC
CVCC
GND
EN
VID0
SREF
1
2
3
4
BOOT
12
11 UGATE
10 PHASE
9 OCSET
CBOOT
QHS
LO
QLS
VIN
3.3V TO 25V
CINC
CINB
RSNS
COCSET
VOUT
0.5V TO 3.3V
COC
COB
RSET1
VCC
RCOMP
CCOMP
RO
RFB
GPIO
FIGURE 3. ISL62873 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
FN6930 Rev 1.00
August 31, 2010
Page 4 of 17

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ISL62873
Application Schematics (Continued)
RVCC
+5V
CPVCC
CVCC
GPIO
EXT_REF
GND
EN
VID0
SREF
1
2
3
4
VCC
12 BOOT
11 UGATE
10 PHASE
9 OCSET
CBOOT
QHS
QLS
LO
COCSET
RCOMP
CCOMP
RO
VIN
3.3V TO 25V
CINC
CINB
VOUT
0.5V TO 3.3V
COC
COB
GPIO
RFB
FIGURE 4. ISL62873 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
FN6930 Rev 1.00
August 31, 2010
Page 5 of 17