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Y8002 Microprocessor
Technical Manual
Systemyde International Corporation

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Every effort has been made to ensure the accuracy of the information contain herein. If you find errors or
inconsistencies please bring them to our attention. In all cases, however, the Verilog HDL source code for
the Y8002 design defines “proper operation”.
Copyright © 2003, 2009, 2012, Systemyde International Corporation. All rights reserved.
Notice:
“Z8000”, “Z8001”, “Z8002” and “Zilog” are registered trademarks of Zilog, Inc. All uses of these terms in
this document are to be construed as adjectives, whether or not the noun “microprocessor”, “CPU” or
“device” are actually present.

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Index
Introduction ........................................................................................................................ 3
Programming Model ........................................................................................................... 5
Addressing and Address Modes ......................................................................................... 9
Instruction Format ............................................................................................................ 13
Instruction Set .................................................................................................................. 15
External Interface and Timing ......................................................................................... 171
Interrupts and Traps ....................................................................................................... 197
Reset ............................................................................................................................... 201
Verilog HDL Source ....................................................................................................... 203
Test Bench ...................................................................................................................... 207
Appendix 1: Execution Details ....................................................................................... 213
Appendix 2: Unimplemented Features/Instructions ........................................................ 225
Appendix 3: Trapped Opcodes ........................................................................................ 229
Appendix 4: Known Timing Differences ........................................................................ 231
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Chapter 1
Introduction
This book documents the operation of the Y8002 microprocessor. The Y8002 design is supplied in Verilog
HDL format and can be implemented in any technology supported by a logic synthesis tool that accepts Ver-
ilog HDL. The design requires roughly 15K logic gate equivalents. Included in the design package is a test
bench that exercises all implemented instructions, flag settings, and representative data patterns. The test
patterns should achieve at least 95% fault coverage.
The Y8002 CPU was designed in a clean-room environment and is a clone of the Zilog Z8002 microproces-
sor. Only publicly available documentation was used to create this design so there may be minor differences
where the public documentation is misleading or lacking. With only a couple of exceptions, the instruction
execution times are identical between the two designs. All known differences for individual instructions are
listed in the instruction description chapter as notes.
The Y8002 design, depending on the version, may not implement all of the instructions, features or operat-
ing modes of the Z8000 architecture. The specific differences, for any given version of the design, are cov-
ered in the various appendices.
The Z8002 CPU is one of four variants of the Z8000 architecture, introduced by Zilog in 1979. The Z8002
and Z8004 support a 16-bit linear address space and are identical except that the Z8004 added support for
virtual memory. The Z8001 and Z8003 support a 23-bit segmented address and are identical except that the
Z8003 added support for virtual memory. All of these devices were implemented in NMOS technology and
the Z8001 CPU and the Z8002 CPU were available for -55C to +125C operation. Manufacturing of these
devices ceased around 1990.
This document should always be used as the final word on the operation of the Y8002 CPU, but it is useful
to refer to the Zilog documentation if the description given here is too cryptic. The Z8000 architecture is
over twenty years old, so it is assumed that it is already at least somewhat familiar to the reader, but an over-
view is presented here. This document will make no attempt to describe the segmented addressing mode of
the Z8000 architecture because it is not present in the Y8002 CPU.
The Z8000 architecture includes sixteen 16-bit general-purpose registers, and uses eight distinct data types
ranging from single bits to 64-bit quadruple words and byte strings. The architecture supports eight different
types of addressing modes. A Z8000 architecture CPU (like the Y8002) has 111 instruction types in its
instruction set. The multiple addressing modes and data types, when coupled with the instruction types, pro-
duces 447 different instructions for the Y8002 processor instruction set.
The architecture includes status signals that can be used to determine the nature of each bus transaction. The
status signals can be decoded and used to implement systems having multiple memory address spaces, each
space being dedicated to a specific purpose.
The architecture includes two operating modes: system mode, and normal mode. This feature allows the
operating system functions to be easily separated from application program functions to enhance operating
system and application data security.
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