Low-voltage single-chip 8-bit microcontrollers
1.0 FUNCTIONAL DESCRIPTION
The 80CL51 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications such as
instrumentation, industrial control, intelligent computer peripherals
and consumer products.
The device provides hardware features, architectural enhancements
and new instructions to function as a controller for applications
requiring up to 64K bytes of program memory and/or up to 64K
bytes of data storage.
The 80CL51 contains a non-volatile 4K byte × 8 read-only program
memory; a static 128 byte × 8 read/write data memory; 32 1/0 lines;
two 16-bit timer/event counters; a thirteen- source two priority-level,
nested interrupt structure and on-chip oscillator and timing circuit.
The device has two software selectable modes of reduced activity
for power reduction: IDLE and Power-down. The Idle mode freezes
the CPU while allowing the RAM, timers, serial I/O and interrupt
system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other chip
functions to be inoperative.
The P80C51 is a 5V version of the low voltage microcontroller
P80CL51. Hereafter the generic term P80CL51 will be used for the
functional description of both types. The special features of the
P80C51 are handled in chapter 1.9.
A machine cycle consists of a sequence of 6 states. Each state time
lasts for two oscillator periods, thus a machine cycle takes 12
oscillator periods or 1µs if the oscillator frequency is 12MHz.
1.1 Memory organization
The 80CL51 has a 4K Program Memory (ROM) plus 128 bytes of
Data Memory (RAM) on board. The device has separate address
spaces for Program and Data Memory (see Memory Map). Using
Ports P0 and P2, the 80CL51 can address up to 64K bytes of
external memory. The CPU generates both read and write signals
(RD and WR) for external Data Memory accesses, and the read
strobe (PSEN) for external Program Memory.
1.1.1 Program Memory
The 80CL51 contains 4K bytes of internal ROM. After reset the CPU
begins execution at location 0000H. The lower 4K bytes of Program
Memory can be implemented in either on- chip ROM or external
Memory. If the EA pin is strapped to VDD, then program memory
fetches from addresses 000H through 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H through FFFFH are
directed to external ROM. Program counter values greater than
0FFFH are automatically addressed to external memory regardless
of the state of the EA pin.
1.1.2 Data Memory
The 80CL51 contains 128 bytes of internal RAM and 25 Special
Function Registers (SFR). The Memory Map below shows the
internal Data Memory space divided into the Lower 128, the Upper
128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as mapped
in Figure 1. The lowest 32 bytes are grouped into 4 banks of 8
registers. Program instructions refer to these registers R0 through
R7. Two bits in the Program Status Word select which register bank
is in use. The next 16 bytes above the register banks form a block of
bit-addressable memory space. The 128 bits in this area can be
directly addressed by the single-bit manipulation instructions. The
remaining registers (30H to 7FH) are directly and indirectly byte
1.1.3 Special Function Registers
The upper 128 bytes are the address locations of the SFRs. Figure
2 shows the Special Function Register (SFR) space. SFRs include
the port latches, timers, peripheral control, serial I/O registers, etc.
These registers can only be accessed by direct addressing. There
are 128 addressable locations in the SFR address space (SFRs with
addresses divisible by eight).
The 80CL51 has five methods for addressing source operands:
– Base-Register-plus Index-Register-indirect
(EA = 1)
(EA = 0)
INTERNAL DATA MEMORY