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Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
FEATURES
Full static 80C51 CPU
8-bit CPU, ROM, RAM, 1/0 in a single 40-lead DIL / mini-pack
4K x 8 ROM, expandable externally to 64K bytes
128 bytes RAM, expandable externally to 64K bytes
Four 8-bit ports, 321/0 lines
Two 16-bit timer / event counters
External memory expandable up to 128K, external ROM up to
64K and / or RAM up to 64K
On-chip oscillator suitable for RC, LC, quartz crystal or ceramic
resonator
Thirteen source, thirteen vector interrupt structure with two priority
levels
Full duplex serial port (UART)
Enhanced architecture with:
non-page oriented instructions
direct addressing
four eight byte RAM register banks
stack depth up to 128 bytes
multiply, divide, subtract and compare instructions
Power-Down and IDLE instructions
Wake-up via external interrupts at Port 1
Single supply voltage of 1.8V to 6.0V (5.0V ±10% for P80C51)
Frequency range of 0 to 16MHz (3.5MHz to 16MHz for P80C51)
Very low current consumption
Operating temperature range: -40 to +85oC
DESCRIPTION
The 80CL51 is manufactured in an advanced CMOS technology.
The instruction set of the 80CL51 is based on that of the 8051. The
80CL51 is a general purpose microcontroller especially suited for
battery-powered applications. The device has low power
consumption and a wide range of supply voltage. For emulation
purposes, the 85CL000 (Piggy-back version) with 256 bytes of RAM
is recommended. The 80CL51 has two software selectable modes
of reduced activity for further power reduction: Idle and Power-down.
The 80CL51 also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 46 two-byte, and 16 three-byte.
The P80CL31 is the ROMless version of the P80CL51. P80C51 is a
5V version of the low voltage P80CL51.
The P80CL31 is the ROMless version of the P80CL51. P80C51 is a
5V version of the low voltage P80CL51.
PIN CONFIGURATIONS
INT2/P1.0 1
INT3/P1.1 2
40 VDD
39 P0.0/AD0
INT4/P1.2 3
38 P0.1/AD1
INT5/P1.3 4
37 P0.2/AD2
INT6/P1.4 5
36 P0.3/AD3
INT7/P1.5 6
35 P0.4/AD4
INT8/P1.6 7
34 P0.5/AD5
INT9/P1.7 8
33 P0.6/AD6
RST 9
RXD/DATA/P3.0 10
PLASTIC
DUAL
IN-LINE
TXD/CLOCK/P3.1 11 AND
SMALL
INT0/P3.2 12
OUTLINE
INT1/P3.3 13 PACKAGES
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
44 43 42 41 40 39 38 37 36 35 34
P1.5/INT7 1
P1.6/INT8 2
P1.7/INT9 3
RST 4
P3.0/RXD 5
NC 6
P3.1/TXD 7
P3.2/INT0 8
P3.3/INT1 9
P3.4/T0 10
P3.5/T1 11
PLASTIC QUAD FLAT PACKAGE
12 13 14 15 16 17 18 19 20 21 22
33 P0.4/AD4
32 P0.5/AD5
31 P0.6/AD6
30 P0.7/AD7
29 EA
28 NC
27 ALE
26 PSEN
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13

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Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
ORDERING INFORMATION
PHILIPS PART ORDER
NUMBER PART MARKING
PHILIPS NORTH AMERICA 1
PART ORDER NUMBER
ROMless
ROM
ROMless
ROM
TEMPERATURE RANGE oC
AND PACKAGE
P80CL31HFP P80CL51HFP P80CL31HFP N P80CL51HFP N
–40 to +85;
40-lead Plastic Dual In-line Package (1.8V to 6V)
P80CL31HFT P80CL51HFT P80CL31HFT D P80CL51HFT D
–40 to +85;
40-lead Plastic Small Outline Package (1.8V to 6V)
P80CL31HFH P80CL51HFH P80CL31HFH B P80CL51HFH B
–40 to +85;
44-lead Plastic Quad Flat Package (1.8V to 6V)
P80C51HFP
P80C51HFP N
–40 to +85;
40-lead Plastic Dual In-line Package (5.0V ±10%)
P80C51HFT
P80C51HFT D
–40 to +85;
40-lead Plastic Small Outline Package (5.0V ±10%)
P80C51HFH
P80C51HFH B
–40 to +85;
44-lead Plastic Quad Flat Package (5.0V ±10%)
NOTE:
1. Parts ordered by the Philips North America part number will be marked with the Philips part marking.
DRAWING
NUMBER
SOT129-1
SOT158-1
SOT307-2
SOT129-1
SOT158-1
SOT307-2

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Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
PIN DESCRIPTIONS
PIN
QFP
DIP
DESIGNATION
40 1 P1.O/INT2
41 2 P1.1/lNT3
42 3 P1.2/lNT4
43 4 P1.3/INT5
44 5 P1.4/lNT6
1 6 P1.5/lNT7
2 7 P1.6/lNT8
3 8 P1.7/lNT9
4 9 RST
5–13 10-17
5 10 P3.0/RXD/data
7 11 P3.1/TXD/clock
8 12 P3.2/lNT0
9 13 P3.3/lNT1
10 14 P3.4/T0
11 15 P3.5/T1
12 16 P3.6/WR
13 17 P3.7/RD
14 18 XTAL2
15 19 XTAL1
16
18-25
20
21-28
Vss
P2.0-P2.7
26 29 PSEN
27 30 ALE
29 31 EA
30-37 32-39 P0.0-P00.7
38 40 VDD
FUNCTION
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 1
output buffer can sink/source 4 LS TTL loads. As inputs, Port 1 pins that are externally pulled LOW
will source current (IlL in the characteristics) due to the internal pullups. Port 1 also serves the
alternative functions INT2 to INT9.
Reset: A high level on this pin for two machine cycles while the oscillator is running resets the
device.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source 4 LS TTL inputs. Port 3 pins that have 1s written to them are pulled HIGH by the
internal pull ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally
pulled LOW will source current (IlL in the characteristics) due to the internal pull ups.
RXD/data: Serial port receiver data input (asynchronous)or data input/output (synchronous)
TXD/clock: Serial port transmitter data output (asynchronous) or clock output (synchronous)
INT0: External interrupt 0.
INT1: External interrupt 1.
T0: Timer 0 external input.
T1: Timer 1 external input.
WR: External data memory write strobe.
RD: External data memory read strobe.
Crystal output: Output of the inverting amplifier of the oscillator. Left open when external clock is
used.
Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally gen-
erated clock source.
Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally
generated clock source.
Ground: Circuit ground potential.
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that have 1s written
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 2
output buffer can sink/source 4 LS TTL loads.
Port 2 emits the high-order address byte during accesses to external memory that use 1 6-bit ad-
dresses (MOVX @DPTR). In this application it uses the strong internal pullups when emitting 1s.
During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
Program store enable output: Read strobe to external program memory. When executing code
out of external program memory, PSEN is activated twice each machine cycle. However, during
each access to external data memory two PSEN activations are skipped.
Address Latch Enable: Output pulse for latching the low byte of the address during access to
external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, and may be
used for external timing or clocking purposes.
External Access: When EA is held High the CPU executes out of internal program memory (un-
less the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of
external memory regardless of the value of the program counter.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8
LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high
impedance inputs. Port 0 is also the multiplexed low order address and data bus during access to
external memory. In this application it uses strong internal pull-ups when emitting logic 1s.
Power supply.

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Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
BLOCK DIAGRAM
FREQUENNCY REFERENCE
XTAL2 XTAL1
COUNTER1
T0 T1
OSCILLATOR
AND TIMING
PROGRAM
MEMORY
(4K BY 8 ROM)
DATA MEMORY
(128 BY 8 RAM)
TWO 16-BIT TIMER/
EVENT COUNTERS
80CL51
CPU
10 3
64K BYTE BUS
EXPANSION
CONTROL
INTERNAL
INTERRUPTS
PROGRAMMABLE
I/O
PROGRAMMABLE
SERIAL PORT,
FULL DUPLEX UART,
SYNCHRONOUS
SHIFT
EXTERNAL ENTERRUPTS1
1. Pins shared with parallels ports pins.
FUNCTIONAL DIAGRAM
CONTROL
PARALLEL PORTS
ADDRESS/DATA BUS
I/O PINS
RXD TXD
(1)
VDD
VSS
RST
XTAL1
XTAL2
PORT 0
ADDRESS AND
DATA BUS
ALTERNATIVE
FUNCTIONS
RxD/data
TxD/clock
INT0
INT1
T0
T1
WR
RD
EA
PSEN
ALE
PORT 3
PORT 1
INT2/INT9
PORT 2
ADDRESS BUS

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Philips Semiconductors
Low-voltage single-chip 8-bit microcontrollers
Product specification
80CL31/80CL51
1.0 FUNCTIONAL DESCRIPTION
General
The 80CL51 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications such as
instrumentation, industrial control, intelligent computer peripherals
and consumer products.
The device provides hardware features, architectural enhancements
and new instructions to function as a controller for applications
requiring up to 64K bytes of program memory and/or up to 64K
bytes of data storage.
The 80CL51 contains a non-volatile 4K byte × 8 read-only program
memory; a static 128 byte × 8 read/write data memory; 32 1/0 lines;
two 16-bit timer/event counters; a thirteen- source two priority-level,
nested interrupt structure and on-chip oscillator and timing circuit.
The device has two software selectable modes of reduced activity
for power reduction: IDLE and Power-down. The Idle mode freezes
the CPU while allowing the RAM, timers, serial I/O and interrupt
system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other chip
functions to be inoperative.
The P80C51 is a 5V version of the low voltage microcontroller
P80CL51. Hereafter the generic term P80CL51 will be used for the
functional description of both types. The special features of the
P80C51 are handled in chapter 1.9.
CPU timing
A machine cycle consists of a sequence of 6 states. Each state time
lasts for two oscillator periods, thus a machine cycle takes 12
oscillator periods or 1µs if the oscillator frequency is 12MHz.
1.1 Memory organization
The 80CL51 has a 4K Program Memory (ROM) plus 128 bytes of
Data Memory (RAM) on board. The device has separate address
spaces for Program and Data Memory (see Memory Map). Using
Ports P0 and P2, the 80CL51 can address up to 64K bytes of
external memory. The CPU generates both read and write signals
(RD and WR) for external Data Memory accesses, and the read
strobe (PSEN) for external Program Memory.
MEMORY MAP
64K
1.1.1 Program Memory
The 80CL51 contains 4K bytes of internal ROM. After reset the CPU
begins execution at location 0000H. The lower 4K bytes of Program
Memory can be implemented in either on- chip ROM or external
Memory. If the EA pin is strapped to VDD, then program memory
fetches from addresses 000H through 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H through FFFFH are
directed to external ROM. Program counter values greater than
0FFFH are automatically addressed to external memory regardless
of the state of the EA pin.
1.1.2 Data Memory
The 80CL51 contains 128 bytes of internal RAM and 25 Special
Function Registers (SFR). The Memory Map below shows the
internal Data Memory space divided into the Lower 128, the Upper
128, and the SFR space.
The lower 128 bytes of the internal RAM are organized as mapped
in Figure 1. The lowest 32 bytes are grouped into 4 banks of 8
registers. Program instructions refer to these registers R0 through
R7. Two bits in the Program Status Word select which register bank
is in use. The next 16 bytes above the register banks form a block of
bit-addressable memory space. The 128 bits in this area can be
directly addressed by the single-bit manipulation instructions. The
remaining registers (30H to 7FH) are directly and indirectly byte
addressable.
1.1.3 Special Function Registers
The upper 128 bytes are the address locations of the SFRs. Figure
2 shows the Special Function Register (SFR) space. SFRs include
the port latches, timers, peripheral control, serial I/O registers, etc.
These registers can only be accessed by direct addressing. There
are 128 addressable locations in the SFR address space (SFRs with
addresses divisible by eight).
1.1.4 Addressing
The 80CL51 has five methods for addressing source operands:
Register
Direct
Register-lndirect
Immediate
Base-Register-plus Index-Register-indirect
EXTERNAL
64K
4096
4095
4095
INTERNAL
(EA = 1)
INTERNAL
(EA = 0)
PROGRAM MEMORY
225
127
INTERNAL
DATA RAM
0
OVERLAPPED
SPACE
SPECIAL
FUNCTION
REGISTERS
INTERNAL DATA MEMORY
0
EXTERNAL
DATA RAM