Figure 2. Write Sequence
"0" A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
When Accessing: X84161 Array: A15–A11=0
X84641 Array: A15–A13=0
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address, up to 32 bytes of
data, and then a special “start nonvolatile write cycle”
The reset sequence is issued ﬁrst (as described in the
Reset Sequence section) to set an internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most signiﬁcant bit ﬁrst, on
the l/O pin. Up to 32 bytes of data are written by issu-
ing a multiple of 8 write cycles. Again, no read cycles
are allowed between writes.
The nonvolatile write cycle is initiated by issuing a spe-
cial read/write “1”/read sequence. The ﬁrst read cycle
ends the page load, then the write “1” followed by a
read starts the nonvolatile write cycle. The device rec-
ognizes 32-byte pages (e.g., beginning at addresses
XXXXXX00000 for X84161).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the ﬁrst address on the
page, where data loading can continue. For this rea-
son, sending more than 256 consecutive data bits will
result in overwriting previous data.
A nonvolatile write cycle will not start if a partial or
incomplete write sequence is issued. The internal write
enable latch is reset when the nonvolatile write cycle is
completed and after an invalid write to prevent inad-
vertent writes. Note that this sequence is fully static,
with no special timing restrictions. The processor is
free to perform other tasks on the bus whenever the
chip enable pin (CE) is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be deter-
mined at any time by simply reading the state of the l/O
pin on the device. This pin is read when OE and CE
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
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Characteristics subject to change without notice. 4 of 17