PRINCIPLES OF OPERATION
Application of power to the X40626 activates a power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP threshold value for
tPURST (200ms nominal) the circuit releases RESET
allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the VCC level
and asserts RESET if supply voltage falls below a preset
minimum VTRIP. The RESET signal prevents the micro-
processor from operating in a power fail or brownout
condition. The RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC
returns and exceeds VTRIP for 200ms.
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The micro-
processor must toggle the SDA pin HIGH to LOW peri-
odically, while SCL is HIGH (this is a start bit) prior to the
expiration of the watchdog time-out period to prevent a
RESET signal. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-progress
communications are terminated. While RESET is active,
no new communications are allowed and no non-volatile
write operation can start. Non-volatile writes in-progress
when RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC/V2MON THRESHOLD RESET PROCEDURE
The X40626 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvola-
tile control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher or
lower voltage value. It is necessary to reset the trip point
before setting the new value.
The VCC and V2MON must be tied together during this
To set the new VTRIP voltage, start by setting the WEL
bit in the control register, then apply the desired VTRIP
threshold voltage to the VCC pin and the programming
voltage, VP, to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the VTRIP programming sequence.
Bring WP LOW to complete the operation.
Figure 1. Set VTRIP Level Sequence (VCC/V2MON = desired VTRIP values, WP = 12-15V when WEL bit set)
WP VP = 12-15V
0 1 23 4 56 7
*for VVTRIP2 address is 0DH
for VTRIP address is 01H
FN8119 Rev 0.00
March 28, 2005
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