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DATASHEET
X40626
64K, 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM
FN8119
Rev 0.00
March 28, 2005
FEATURES
• Dual voltage monitoring
—V2Mon operates independent of VCC
• Watchdog timer with selectable timeout intervals
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—User programmable VTRIP threshold
—Reset signal valid to VCC=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lockprotection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time-
out interval, the device activates the RESET signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
BLOCK DIAGRAM
V2MON
WP
SDA
SCL
S0
S1
VCC
V2 Monitor
Logic
+
VTRIP2
-
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
64KB
EEPROM
Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
VTRIP
+
-
Power-on and
Low Voltage
Reset
Generation
V2FAIL
RESET
FN8119 Rev 0.00
March 28, 2005
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X40626
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the set minimum VCC trip point.
RESET is asserted until VCC returns to proper operating
level and stabilizes. Four industry standard Vtrip thresholds
are available. However, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom require-
ments or to fine-tune the threshold for applications requir-
ing higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block LockProtection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software protocol
allowing operation on an I2C bus.
PIN FUNCTION
The device utilizes Intersil’s proprietary Direct Writecell,
providing a minimum endurance of 100,000 page write
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC
S0
S1
NC
RESET
NC
VSS
1
2
3
4
5
6
7
14 VCC
13 NC
12 WP
11 V2MON
10 V2FAIL
9 SCL
8 SDA
Pin
1, 4, 6, 13
2
3
5
7
8
9
10
11
12
14
Name
NC
S0
S1
RESET
VSS
SDA
SCL
V2FAIL
V2MON
WP
VCC
Function
No Internal Connections
Device Select Input
Device Select Input
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the mini-
mum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes
active on power-up and remains active for typically 200ms after the power supply
stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This
pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2
and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on
this pin. This circuit works independently from the Low VCC reset and battery switch circuits.
Connect V2FAIL to VSS when not used.
V2 Voltage
goes LOW.
Monitor Input. When
This input can monitor
the
an
V2MON input is less than
unregulated power supply
twhiethVaTnRIePx2tevornltaalgree,sVis2toFrAIL
divider or can monitor a second power supply with no external components. Connect V2MON
to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control reg-
ister.
Supply Voltage
FN8119 Rev 0.00
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X40626
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X40626 activates a power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When VCC exceeds the device VTRIP threshold value for
tPURST (200ms nominal) the circuit releases RESET
allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the VCC level
and asserts RESET if supply voltage falls below a preset
minimum VTRIP. The RESET signal prevents the micro-
processor from operating in a power fail or brownout
condition. The RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC
returns and exceeds VTRIP for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The micro-
processor must toggle the SDA pin HIGH to LOW peri-
odically, while SCL is HIGH (this is a start bit) prior to the
expiration of the watchdog time-out period to prevent a
RESET signal. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-progress
communications are terminated. While RESET is active,
no new communications are allowed and no non-volatile
write operation can start. Non-volatile writes in-progress
when RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
VCC/V2MON THRESHOLD RESET PROCEDURE
The X40626 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or if
higher precision is needed in the VTRIP value, the
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvola-
tile control signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher or
lower voltage value. It is necessary to reset the trip point
before setting the new value.
The VCC and V2MON must be tied together during this
sequence.
To set the new VTRIP voltage, start by setting the WEL
bit in the control register, then apply the desired VTRIP
threshold voltage to the VCC pin and the programming
voltage, VP, to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the VTRIP programming sequence.
Bring WP LOW to complete the operation.
Figure 1. Set VTRIP Level Sequence (VCC/V2MON = desired VTRIP values, WP = 12-15V when WEL bit set)
WP VP = 12-15V
SCL
01234567 01234567
0 1 23 4 56 7
0123456 7
SDA
A0H
00H xxH*
*for VVTRIP2 address is 0DH
for VTRIP address is 01H
00H
FN8119 Rev 0.00
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X40626
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” volt-
age level. For example, if the current VTRIP is 4.4V and
the new VTRIP must be 4.0V, then the VTRIP must be
reset. When VTRIP is reset, the new VTRIP is something
less than 1.7V. This procedure must be used to set the
voltage to a lower value.
To reset the new VTRIP voltage start by setting the WEL
bit in the control register, apply the desired VTRIP thresh-
old voltage to the VCC pin and the programming voltage,
VP, to the WP pin and 2 byte address and 1 byte of “00”
data. The stop bit of a valid write operation initiates the
VTRIP programming sequence. Bring WP LOW to com-
plete the operation.
Figure 2. Reset VTRIP Level Sequence (VCC/V2MON > 3V, WP = 12-15V, WEL bit set)
WP
SCL
VP = 12-15V
01234567 01234567
0 1 23 4 56 7
0123456 7
SDA
A0H
Figure 3. Sample VTRIP Reset Circuit
VTRIP
Adj.
4.7K
RESET
00H xxH*
*for VTRIP2 address is 0FH
for VTRIP address is 03H
00H
1 14
2 13
3 12
4
5
X40626
69
78
Adjust
VP
Run
µC
SCL
SDA
FN8119 Rev 0.00
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X40626
Figure 4. VTRIP Programming Sequence
VTRIPX Programming
No
Desired
VTRIPX
Present Value
YES
Set VX = Desired VTRIPX
New VX applied =
Old VX applied + | Error |
NO
Execute
Set Higher VTRIPX Sequence
Execute
Set Higher VX Sequence
Apply VCC and Voltage
> Desired VTRIPX to VX
Decrease VX
Vx = VCC, V2MON
Let: MDE = Maximum Desired Error
MDE+
Desired Value
MDE
Acceptable
Error Range
Error = Actual - Desired
New VX applied =
Old VX applied - | Error |
Execute Reset VTRIPX
Sequence
Error < MDE
Output Switches?
YES
Actual VTRIPX -
Desired VTRIPX
Error > MDE+
| Error | < | MDE |
DONE
FN8119 Rev 0.00
March 28, 2005
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