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X4003, X4005
CPU Supervisor
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DATASHEET
FN8113
Rev 2.00
June 30, 2008
These devices combine three popular functions; Power-on
Reset Control, Watchdog Timer and Supply Voltage
Supervision. This combination lowers system cost, reduces
board space requirements and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Five industry standard VTRIP
thresholds are available; however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements, or to fine-tune the threshold for applications
requiring higher precision.
Block Diagram
Features
• Selectable watchdog timer
- Select 200ms, 600ms, 1.4s, off
• Low VCC detection and reset assertion
- Five standard reset threshold voltages nominal 4.62V,
4.38V, 2.92V, 2.68V, 1.75V
- Adjust low VCC reset threshold voltage using special
programming sequence
- Reset signal valid to VCC = 1V
• Low power CMOS
- 12µA typical standby current, watchdog on
- 800nA typical standby current watchdog off
- 3mA active current
• 400kHz I2C interface
• 1.8V to 5.5V power supply operation
• Available packages
- 8 Ld SOIC
- 8 Ld MSOP
• Pb-free available (RoHS compliant)
Pinout
X4003, X4005
(8 LD SOIC, MSOP)
TOP VIEW
NC
NC
RESET/RESET*
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
*RESET APPLIES TO X4003
RESET APPLIES TO X4005
WP
SDA
SCL
VCC
WATCHDOG TRANSITION
DETECTOR
DATA
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
VCC THRESHOLD
RESET LOGIC
CONTROL
REGISTER
VTRIP
+
-
WATCHDOG
TIMER RESET
RESET AND
WATCHDOG
TIMEBASE
POWER-ON AND
LOW VOLTAGE
RESET
GENERATION
RESET (X4003)
RESET (X4005)
FN8113 Rev 2.00
June 30, 2008
Page 1 of 16

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X4003, X4005
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
PART VCC RANGE VTRIP RANGE TEMP. RANGE
MARKING
(V)
(V)
(°C)
PACKAGE PKG. DWG. #
X4003M8-4.5A ACH
X4005M8-4.5A ACQ
4.5 to 5.5 4.5 to 4.75
0 to +70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z-4.5A DAH
(Note)
X4005M8Z-4.5A DAP
(Note)
0 to +70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8-4.5A X4003 AL X4005S8-4.5A X4005 AL
0 to +70
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z-4.5A X4003 ZAL X4005S8Z-4.5A X4005 ZAL
(Note)
(Note)
0 to +70
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8I-4.5A ACI
X4005M8I-4.5A ACR
-40 to +85 8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-4.5A DAD
(Note)
X4005M8IZ-4.5A DAM
(Note)
-40 to +85 8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8I-4.5A X4003 AM X4005S8I-4.5A X4005 AM
-40 to +85 8 Ld SOIC
(150 mil)
MDP0027
X4003S8IZ-4.5A X4003 ZAM X4005S8IZ-4.5A X4005 ZAM
(Note)
(Note)
-40 to +85 8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8
ACJ X4005M8 ACS
4.25 to 4.5
0 to +70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z (Note) DAE
X4005M8Z (Note) DER
0 to +70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8
X4003
X4005S8
X4005
0 to +70
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z (Note) X4003 Z X4005S8Z (Note) X4005 Z
0 to +70
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8I
ACK
X4005M8I
ACT
-40 to +85 8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ (Note) DAA
X4005M8IZ
(Note)
DAJ
-40 to +85 8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8I
X4003 I X4005S8I
X4005 I
-40 to +85 8 Ld SOIC
(150 mil)
MDP0027
X4003S8IZ (Note) X4003 ZI X4005S8IZ
(Note)
X4005 ZI
-40 to +85 8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8-2.7A ACL
X4005M8-2.7A ACU
2.7 to 5.5 2.85 to 3.0
0 to +70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z-2.7A DAG
(Note)
X4005M8Z-2.7A DAO
(Note)
0 to +70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8-2.7A X4003 AN X4005S8-2.7A X4005 AN
0 to +70
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z-2.7A X4003 ZAN X4005S8Z-2.7A X4005 ZAN
(Note)
(Note)
0 to +70
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8-2.7
ACN
X4005M8-2.7 ACW
2.55 to 2.7
0 to +70
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z-2.7
(Note)
DAF
X4005M8Z-2.7 DAN
(Note)
0 to +70
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
X4003S8-2.7
X4003 F X4005S8-2.7
X4005 F
0 to +70
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z-2.7
(Note)
X4003 ZF X4005S8Z-2.7
(Note)
X4005 ZF
0 to +70
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
FN8113 Rev 2.00
June 30, 2008
Page 2 of 16

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X4003, X4005
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
PART
MARKING
PART NUMBER
RESET
(ACTIVE HIGH)
PART VCC RANGE VTRIP RANGE TEMP. RANGE
MARKING
(V)
(V)
(°C)
PACKAGE
X4003S8I-2.7A X4003 AP X4005S8I-2.7A X4005 AP 2.7 to 3.6 2.85 to 3.0
-40 to +85 8 Ld SOIC
(150 mil)
PKG. DWG. #
MDP0027
X4003S8IZ-2.7A X4003 ZAP X4005S8IZ-2.7A X4005 ZAP
(Note)
(Note)
-40 to +85 8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8I-2.7A ACM
X4005M8I-2.7A ACV
-40 to +85 8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-2.7A DAC
(Note)
X4003S8I-2.7
X4003 G
X4005M8IZ-2.7A DAL
(Note)
X4005S8I-2.7 X4005 G
X4003S8IZ-2.7
(Note)
X4003 ZG X4005S8IZ-2.7 X4005 ZG
(Note)
2.55 to 2.7
-40 to +85
-40 to +85
-40 to +85
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
X4003M8I-2.7 ACO
X4005M8I-2.7 ACX
-40 to +85 8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ-2.7 DAB
(Note)
X4005M8IZ-2.7 DAK
(Note)
-40 to +85 8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
Pin Descriptions
PIN
NUMBER
(MSOP)
NAME
FUNCTION
1 NC No internal connections
2 NC No internal connections
3 RESET/RESET Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below
the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms.
RESET/RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the
selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a
stop condition resets the watchdog timer. RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
4 VSS Ground
5
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop
condition resets the watchdog timer. The absence of this procedure within the watchdog time-out period results in
RESET/RESET going active.
6 SCL Serial Clock. The serial clock controls the serial bus timing for data input and output.
7 WP Write Protect. WP HIGH prevents changes to the watchdog timer setting.
8 VCC Supply voltage
FN8113 Rev 2.00
June 30, 2008
Page 3 of 16

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X4003, X4005
Principles of Operation
Power-on Reset
Application of power to the X4003/X4005 activates a power-on
reset circuit that pulls the RESET/RESET pin active. This signal
provides several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to stabilization
of the oscillator.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
When VCC exceeds the device VTRIP threshold value for 200ms
(nominal) the circuit releases RESET/RESET, allowing the
system to begin operation.
Low Voltage Monitoring
During operation, the X4003/X4005 monitors the VCC level and
asserts RESET/RESET if supply voltage falls below a preset
minimum VTRIP. The RESET/RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC returns
and exceeds VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the SDA and SCL pins. The microprocessor
must toggle the SDA pin HIGH to LOW periodically, while SCL
also toggles from HIGH to LOW (this is a start bit) followed by a
stop condition prior to the expiration of the watchdog time-out
period to prevent a RESET/RESET signal. The state of two
nonvolatile control bits in the control register determine the
watchdog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP pin
HIGH.
SCL
0.6µs
0.6µs
SDA
START
CONDITION
RESTART
STOP
CONDITION
FIGURE 1. WATCHDOG RESTART
VCC Threshold Reset Procedure
The X4003/X4005 is shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications
where the standard VTRIP is not exactly right, or if higher
precision is needed in the VTRIP value, the X4003/X4005
threshold may be adjusted. The procedure is described in the
following and uses the application of a nonvolatile control
signal.
Setting the VTRIP Voltage
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it is
necessary to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP threshold
voltage to the VCC pin and tie the WP pin to the programming
voltage VP. Then write data 00hto address 01h. The stop bit
following a valid write operation initiates the VTRIP programing
sequence. Bring WP LOW to complete the operation.
WP VP = 15V TO 18V
SCL
0 1 2 34 56 7
0 1 23 4 56 7
0 1 23 4 56 7
SDA
A0h
01h 00h
FIGURE 2. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE)
FN8113 Rev 2.00
June 30, 2008
Page 4 of 16

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X4003, X4005
WP
SCL
SDA
VP = 15V TO 18V
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
A0h 03h 00h
FIGURE 3. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15V TO 18V)
VTRIP
ADJ.
RESET/RESET
4.7k
18
2
X4003
X4005
7
36
45
ADJUST
VP
RUN
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
Resetting the VTRIP Voltage
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP
is reset, the new VTRIP is something less than 1.7V. This
procedure must be used to set the voltage to a lower value.
To reset the new VTRIP voltage, apply the desired VTRIP
threshold voltage to the VCC pin and tie the WP pin to the
programming voltage VP. Then write 00h to address 03h. The
stop bit of a valid write operation initiates the VTRIP
programming sequence. Bring WP LOW to complete the
operation.
µC
SCL
SDA
FN8113 Rev 2.00
June 30, 2008
Page 5 of 16