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DATASHEET
X40010, X40011, X40014, X40015
Dual Voltage Monitor with Integrated CPU Supervisor
FN8111
Rev 0.00
March 28, 2005
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms,
200ms,1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
— Computers
—Network Servers
DESCRIPTION
The X40010/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
SDA
SCL
VCC
(V1MON)
V2MON
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
Fault Detection
Register
Status
Register
Watchdog Timer
and
Reset Logic
User Programmable
VTRIP1
User Programmable
VTRIP2
+
-
V2MON
+ VCC
Power on,
Low Voltage
Reset
Generation
-
*X40010/11 = V2MON*
X40014/15 = VCC
WDO
RESET
X40010/14
RESET
X40011/15
V2FAIL
FN8111 Rev 0.00
March 28, 2005
Page 1 of 24

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X40010, X40011, X40014, X40015
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second voltage monitor
circuit tracks the unregulated supply to provide a power
fail warning or monitors different power supply voltage.
Three common low voltage combinations are available,
however, Intersil’s unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The device features a 2-wire interface and software pro-
tocol allowing operation on an I2C® bus.
Dual Voltage Monitors
Device
X40010/11
-A
-B
-C
X40014/15
-A
-B
-C
Expected System Voltages
5V; 3V or 3.3V
5V; 3V
3V; 3.3V; 1.8V
3V; 3.3V; 1.5V
3V; 1.5V
3V or 3.3V; 1.1 or 1.2V
Table 1:
Vtrip1(V)
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.85–2.95*
2.0–4.75*
2.85–2.95*
2.55–2.65*
2.85–2.95*
Vtrip2(V)
1.70–4.75
2.85–2.95
2.55–2.65
1.65–1.75
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
POR (system)
RESET = X40010
RESET = X40011
RESET = X40014
RESET = X40015
*Voltage monitor requires VCC to operation. Others are independent of VCC.
PIN CONFIGURATION
X40010/14, X40011/15
8-Pin SOIC
V2FAIL
V2MON
RESET/RESET
VSS
1
2
3
4
8 VCC
7 WDO
6 SCL
5 SDA
PIN DESCRIPTION
X40010/14, X40011/15
8-Pin TSSOP
WDO
VCC
V2FAIL
V2MON
1
2
3
4
8 SCL
7 SDA
6 VSS
5 RESET/RESET
Pin
SOIC TSSOP Name
Function
1 3 V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2 4 V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect
not used.The V2MON comparator is supplied by V2MON (X40010/11)
V2MON to VSS
or by VCC Input
(oXr4V0C0C14w/1h5e)n.
3 5 RESET/ RESET Output. (X40011/15) This is an active LOW, open drain output which goes active whenever
RESET VCC falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.
RESET Output. (X40010/14) This is an active HIGH CMOS output which
falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and
goes active whenever VCC
for the tPURST thereafter.
4 6 VSS Ground
5 7 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to
LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transi-
tion within the watchdog time out period results in WDO going active.
FN8111 Rev 0.00
March 28, 2005
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X40010, X40011, X40014, X40015
PIN DESCRIPTION (Continued)
Pin
SOIC TSSOP
68
71
82
Name
SCL
WDO
VCC
Function
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
Supply Voltage
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X40010/11/14/15 activates a
Power On Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabiliza-
tion of the oscillator.
– It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP1 threshold value for
tPURST (selectable) the circuit releases the RESET
(X40011) and RESET (X40010) pin allowing the system to
begin operation.
For the X40014/15 devices, the V2FAIL signal remains
actice until VCC drops below 1Vx and remains active until
V2MON returns and exceeds VTRIP2. This sense circuitry
is powered by VCC. If VCC = 0, V2MON cannot be moni-
tored.
Figure 1. Two Uses of Multiple Voltage Monitoring
X40011-A
VCC V2MON
6–10V
1M
1M
5V
Reg
VCC
RESET
V2MON
(2.9V)
V2FAIL
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
Low Voltage VCC (V1 Monitoring)
During operation, the X40010/11/14/15 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP1. The RESET/RESET sig-
nal prevents the microprocessor from operating in a
power fail or brownout condition. The V1FAIL signal
remains active until the voltage drops below 1V. It also
remains active until VCC returns and exceeds VTRIP1 for
tPURST.
Low Voltage V2 Monitoring
The X40010/11/14/15 also monitors a second voltage level
and asserts V2FAIL if the voltage falls below a preset
minimum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating in a
power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. For the X40010/11 the V2FAIL signal remains
active until the VCC drops below 1V (VCC falling). It also
remains active until V2MON returns and exceeds VTRIP2
by 0.2V. This voltage sense circuitry monitors the power
supply connected to the V2MON pin. If VCC = 0, V2MON
can still be monitored.
Unreg.
Supply
3.3V
Reg
1.2V
Reg
X40014-C
VCC
VCC
RESET
V2MON
V2FAIL
System
Reset
Notice: No external components required to monitor two voltages.
FN8111 Rev 0.00
March 28, 2005
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X40010, X40011, X40014, X40015
Figure 2. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2)
WDO
SCL
0
70
VCC/V2MON
VP
70
7
SDA
A0h
00h tWC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The micro-
processor must toggle the SDA pin HIGH to LOW periodi-
cally, while SCL also toggles from HIGH to LOW (this is a
start bit) followed by a stop condition prior to the expiration
of the watchdog time out period to prevent a WDO signal
going active. The state of two nonvolatile control bits in the
Status Register determines the watchdog timer period. The
microprocessor can change these watchdog bits by writing
to the X40010/11/14/15 control register (also refer to page
19).
Figure 3. Watchdog Restart
.6µs 1.3µs
SCL
SDA
Timer Start
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40010/11/14/15is shipped with standard V1 and
V2 threshold (VTRIP1, VTRIP2) voltages. These values will
not change over normal operating and storage condi-
tions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X40010/11/14/15trip
points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting a VTRIPx Voltage (x = 1, 2)
There are two procedures used to set the threshold volt-
ages (VTRIPx), depending if the threshold voltage to be
stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly into
the VTRIPx cell. If however, the new setting is to be lower
than the present setting, then it is necessary to “reset” the
VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x = 1, 2)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin Vcc(V1MON), or V2MON. The
Vcc(V1MON) and V2MON must be tied together during
this sequence. Then, a programming voltage (Vp) must
be applied to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h, followed by the Byte Address 01h for
VTRIP1 and 09h for VTRIP2, and a 00h Data Byte in order
to program VTRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation.
Note: This operation does not corrupt the memory array.
Setting a Lower VTRIPx Voltage (x = 1, 2)
In order to set VTRIPx to a lower voltage than the present
value, then VTRIPx must first be “reset” according to the
procedure described below. Once VTRIPx has been
“reset”, then VTRIPx can be set to the desired voltage
using the procedure described in “Setting a Higher
VTRIPx Voltage”.
FN8111 Rev 0.00
March 28, 2005
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X40010, X40011, X40014, X40015
Resetting the VTRIPx Voltage
To reset a VTRIPx voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
VTRIP1 and 0Bh for VTRIP2, followed by 00h for the Data
Byte in order to reset VTRIPx. The STOP bit following a
valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to com-
plete the operation.
After being reset, the value of VTRIPx becomes a nomi-
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory array.
CONTROL REGISTER
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 7.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, BP1, and BP0. The
X40010/11/14/15 will not acknowledge any data bytes
written after the first byte is entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
765 4
PUP1 WD1 WD0 BP
3 210
0 RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 4. Sample VTRIP Reset Circuit
VTRIP1
Adj.
V2FAIL
RESET
VTRIP2
Adj.
4.7K
1
3 SOIC
2 X4001x
4
8
7
6
5
Adjust
VP
Run
µC
SCL
SDA
FN8111 Rev 0.00
March 28, 2005
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