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Replaces X25643/X25645
X5643/X5645
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low VCC reset threshold voltage
using special programming sequence
—Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lockprotection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—8-lead PDIP, 14-lead SOIC
BLOCK DIAGRAM
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers sys-
tem cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even after
cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the minimum VCC
trip point. RESET/RESET is asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however,
Xicor’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
WP
SI
SO
SCK
CS/WDI
VCC
Watchdog Transition
Detector
Protect Logic
Data
Register
Command
Decode &
Control
Logic
Status
Register
16Kbits
16Kbits
VCC Threshold
Reset logic
32Kbits
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power On and
Low Voltage
Reset
Generation
RESET/RESET
X5643 = RESET
X5645 = RESET
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X5643/X5645
PIN CONFIGURATION
CS/WDI
SO
WP
VSS
8-Lead PDIP
18
27
3 X5643/45 6
45
VCC
RESET/RESET
SCK
SI
NC
CS/WDI
CS/WDI
SO
WP
VSS
NC
14-Lead SOIC
1 14
2 13
3 12
4 X5643/45 11
5 10
69
78
NC
VCC
VCC
RESET/RESET
SCK
SI
NC
Pin
PDIP
1
2
5
6
3
4
8
7
Pin
SOIC
2&3
Pin
TSSOP
2
Name
CS/WDI
4 3 SO
9 13 SI
10 14 SCK
5 7 WP
6 8 VSS
12 & 13 19
VCC
11 18 RESET/
RESET
1, 7, 8, 1, 4–6,
14 9–12,
15–17, 20
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is
at a high impedance state. Unless a nonvolatile write cycle is underway, the
device will be in the standby power mode. CS LOW enables the device, plac-
ing it in the active power mode. Prior to the start of any operation after power
up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin.The rising edge of the serial clock (SCK) latches the in-
put data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever VCC falls below the minimum VCC sense level.
It will remain active until VCC rises above the minimum VCC sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET
goes active on power up at about 1V and remains active for 200ms after the
power supply stabilizes.
No internal connections
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X5643/X5645
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5643/X5645 activates a
power on reset circuit. This circuit goes active at about
1V and pulls the RESET/RESET pin active. This signal
prevents the system microprocessor from starting to
operate with insufficient voltage or prior to stabilization
of the oscillator. When VCC exceeds the device VTRIP
value for 200ms (nominal) the circuit releases RESET/
RESET, allowing the processor to begin executing code.
Low Voltage Monitoring
During operation, the X5643/X5645 monitors the VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum VTRIP. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The RESET/RESET
signal remains active until the voltage drops below 1V.
It also remains active until VCC returns and exceeds
VTRIP for 200ms.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microproces-
sor must toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits
in the status register determine the watchdog timer
period. The microprocessor can change these watchdog
bits, or they may be “locked” by tying the WP pin LOW
and setting the WPEN bit HIGH.
VCC Threshold Reset Procedure
The X5643/X5645 has a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard VTRIP is not exactly right, or
for higher precision in the VTRIP value, the X5643/
X5645 threshold may be adjusted.
Setting the VTRIP Voltage
This procedure sets the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the
new VTRIP is 4.6V, this procedure directly makes the
change. If the new setting is lower than the current set-
ting, then it is necessary to reset the trip point before
setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the Vcc pin and tie the CS/WDI pin and the
WP pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage VP
to both SCK and SI and pulse CS/WDI LOW then
HIGH. Remove VP and the sequence is complete.
Figure 1. Set VTRIP Voltage
CS
VP
SCK
VP
SI
Resetting the VTRIP Voltage
This procedure sets the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the
VTRIP is reset, the new VTRIP is something less than
1.7V. This procedure must be used to set the voltage to
a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7
and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP
pin, and the SCK pin HIGH. RESET/RESET and SO
pins are left unconnected. Then apply the programming
voltage VP to the SI pin ONLY and pulse CS/WDI LOW
then HIGH. Remove VP and the sequence is complete.
Figure 2. Reset VTRIP Voltage
CS
SCK VCC
VP
SI
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X5643/X5645
Figure 3. VTRIP Programming Sequence Flow Chart
VTRIP Programming
New VCC Applied =
Old VCC Applied + Error
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 10mV)
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
NO
RESET pin
goes active?
YES
Error Emax
Emax = Maximum Desired Error
Measured VTRIP -
Desired VTRIP
Error > Emax
Error < Emax
DONE
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X5643/X5645
Figure 4. Sample VTRIP Reset Circuit
VTRIP
Adj.
Program
4.7K
+
NC
18
27
3 X5643/45 6
45
NC 4.7K
RESET
NC
VP
10K 10K
Reset VTRIP
Test VTRIP
Set VTRIP
SPI SERIAL MEMORY
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the status regis-
ter. The status register may be read at any time, even dur-
ing a write cycle.The status register is formatted as follows:
7 65 43210
WPEN FLB WD1 WD0 BL1 BL0 WEL WIP
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
WREN
SFLB
0000 0110
0000 0000
WRDI/RFLB
0000 0100
RSDR
WRSR
0000 0101
0000 0001
READ
WRITE
0000 0011
0000 0010
Operation
Set the write enable latch (enable write operations)
Set flag bit
Reset the write enable latch/reset flag bit
Read status register
Write status register (watchdog, block lock, WPEN & flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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