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ESD PROTECTION DEVICE
L02U5V0NA-4C
STAND-OFF VOLTAGE - 5.0 Volts
POWER DISSIPATION - 20 Watts
GENERAL DESCRIPTION
The L02U5V0NA-4C is ultra low capacitance TVS arrays
designed to protect high speed data interfaces. This series
has been specifically designed to protect sensitive
components which are connected to high-speed data and
transmission lines from overvoltage caused by ESD
(electrostatic discharge), CDE (Cable Discharge Events),
and EFT (electrical fast transients).
FEATURES
• Protects four I/O lines (Data line)
• Max. peak pulse power: Ppp=20w at tp = 8/20 us.
• Low capacitance: 0.28pF typical (I/O to I/O)
• IEC 61000-4-2 ,30KV(air);>±16KV(contact)
• Qualified to AEC-Q101 Rev_C
MECHANICAL DATA
• Case material:“Green”molding compound UL flammability
classification 94V-0 (No Br, Sb, Cl)
• Terminals: lead free plating
• Component in accordance to RoHs 2011/65/EU
APPLICATION
• High definition multi-media interface (HDMI)
1.3 & 1.4 and 2.0 version
• Digital visual interface (DVI)
• Display protTM interface
• SATA and ESATA interface
• USB 3.0 / 3.1
• Desktop and Notebooks PCs
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
Ratings at 25°C ambient temperature unless otherwise specified.
ABSOLUTE RATINGS
PARAMETER
Peak pulse power (tp = 8/20us)
Peak pulse current (tp = 8/20us)
Operating junction temperature range
Storage temperature range
Soldering temperature, t max = 10s
ELECTRICAL CHARACTERISTICS
PARAMETER
Reverse standoff voltage
Reverse leakage current
Breakdown voltage
Clamping Voltage
Junction capacitance
TEST CONDITIONS
Any I/O pin to ground
VDRM = 5V, Any I/O pin to ground
IR = 1 mA
Ipp=1A, tp = 8/20 us
VR = 0~2.5V, f = 1MHz, between I/O pins
VR = 0~2.5V, f = 1MHz, any I/O pin to ground
SYMBOL
Ppk
Ipp
TJ
TSTG
TL
SYMBOL
VRWM
IRM
VBR
Vc
CJ
SLP2510P8
SLP2510P8
DIM. MIN.
MAX.
A 0.45 0.55
A1 0.00
0.05
A3 0.152 REF.
D 2.45 2.55
E 0.95 1.05
D1 0.35
0.45
E1 0.35
0.45
b 0.15 0.25
e 0.50 BSC
L 0.35 0.45
All dimension in millimeter
PIN ASSIGNMENT
1,2,4,5
6,7,9,10
Input lines
NC
3,8 Ground
VALUE
20
1.5
-55 to +125
55 to +150
260
UNIT
W
A
°C
°C
°C
MIN
TYP.
MAX
UNIT
-- -- 5.0 V
-- -- 0.5 uA
6.0 -- 9.0 V
-- -- 11 V
-- 0.28 0.3
pF
-- 0.43 0.5
Rev. 1, Oct-2017, KSIR94

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RATING AND CHARACTERISTIC CURVES
L02U5V0NA-4C
Figure 1. 8/20 us pulse waveform
according to IEC 61000-4-5
1000
100
TJ =25°C, tp (us) = 8/20 us
exponentially decay waveform
10
1
1 10 100 1000
Pulse Time(us)
Figure 3. Power Dissipation versus Pulse Time
2
Any I/O pin to ground
TJ =25°C, f=1MHz, Level=100mV
1
0
012345
Reverse Voltage (V)
Figure 5. Typical Junction Capacitance
Figure 2. ESD pulse waveform
according to IEC 61000-4-2
1.2
0.8
0.4
0
0 25 50 75 100 125 150
Junction Temperature ()
Figure 4. Peak pulse power versus TJ
100.0
10.0
1.0
0.1
0
25 50 75 100
Junction Temperature ()
125
Figure 6. Reverse Leakage Current versus TJ

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RATING AND CHARACTERISTIC CURVES
L02U5V0NA-4C
I/O1
+/-8KV
ESD Contact
discharge
V (i/o)
Figure 7. ESD Test Configuration
Figure 8. Clamped +8 kV ESD voltage waveform
Figure 9. Clamped -8 kV ESD voltage waveform
Transmission Line Pulsing (TLP) Measurement
18
16
14
12
10
8
6
4
2 I/OI/OtotoGGnndd
0
0 2 4 6 8 10 12 14 16 18 20 22 24 26
Transmission Line Pulsing (TLP) Voltage (V)

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APPLICATION INFORMATION
L02U5V0NA-4C
DisplayPort
Connector
I/O 1 1 .. .. ..10 NC
I/O 2 NC
2 .. .. .. 9
GND 3
8 GND
I/O 3 NC
4 .. .. .. 7
I/O 4 5 .. .. .. 6 NC
LL0052EUS5DVL05NVA0N-4AC-4
I/O 1 1 .. .. ..10 NC
I/O 2 2 .. .. .. 9 NC
GND 3
8 GND
I/O 3 NC
4 .. .. .. 7
I/O 4 5 .. .. .. 6 NC
LL0052EUS5DVL05NVA0N-4AC-4
Figure 10. Display Port ESD Protection
ML Lane0 +
ML Lane0 -
ML Lane1 +
ML Lane1 -
ML Lane2 +
ML Lane2 -
ML Lane3 +
ML Lane3 -
MDDI Data0+
MDDI Data0-
MDDI Link
Controller
( HOST )
MDDI Data1+
MDDI Data1-
MDDI Stb+
MDDI Stb-
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L0L50E2US5DVL05NVA0-4NCA-4
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L0L50E2SUD5VL05NVA0-N4CA-4
MDDI Data0+
MDDI Data0-
MDDI Data1+
MDDI Data1-
MDDI Stb+
MDDI Stb-
MDDI Link
Controller
( Client )
Figure 11. MDDI Interface ESD Protection

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APPLICATION INFORMATION
L02U5V0NA-4C
LVDS
Data
Input
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L0L50E2US5DVL05NVA-04NCA-4
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
LL0052EUS5VD0LN5AV-40CNA-4
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
LVDS
Data
Output
OUT4+
OUT4-
Figure 12. LVDS Interface ESD Protection
A+
SATA
A-
Connector B+
B-
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L0L50E2US5DVL05NVA0-N4CA-4
A+
A-
STAT
B+ Controller
B-
Figure 13. Serial ATA ESD Protection