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ESD PROTECTION DEVICE
L05ESDL5V0NA-4
STAND-OFF VOLTAGE - 5.0 Volts
POWER DISSIPATION - 50 Watts
GENERAL DESCRIPTION
The L05ESDL5V0NA-4 is ultra low capacitance TVS
arrays designed to protect high speed data interfaces.
This series has been specifically designed to protect
sensitive components which are connected to high-speed
data and transmission lines from over voltage caused by
ESD (electrostatic discharge), CDE (Cable Discharge
Events), and EFT (electrical fast transients).
FEATURES
• Flow-through design
• Protects four I/O lines (Data line)
• Max. peak pulse power: Ppp=50w at tp = 8/20 us.
• Low capacitance: 0.3pF typical (I/O to I/O)
• IEC 61000-4-2, level 4 (ESD), 15KV(air)
;>±8KV(contact)
MECHANICAL DATA
• Case material: “Green” molding compound UL
flammability classification 94V-0 (No Br, Sb, Cl),
Halogen-free”
• Terminals: lead free plating ( matte tin finish )
• Component in accordance to RoHs 2002/95/EC
APPLICATION
• High definition multi-media interface (HDMI)
• Digital visual interface (DVI)
• Display protTM interface
• MDDI ports
• LVDS
• Serial ATA
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
Ratings at 25°C ambient temperature unless otherwise specified.
ABSOLUTE RATINGS
PARAMETER
Peak pulse power (tp = 8/20us)
Peak pulse current (tp = 8/20us)
Operating junction temperature range
Storage temperature range
Soldering temperature, t max = 10s
ELECTRICAL CHARACTERISTICS
SYMBOL
Ppk
Ipp
TJ
TSTG
TL
PARAMETER
Reverse standoff voltage
Reverse leakage current
Breakdown voltage
Forward voltage
Clamping Voltage
Junction capacitance
TEST CONDITIONS
Any I/O pin to ground
VDRM = 5V
IR = 1 mA
IF = 15 mA, pin 3,8 to pin 1,2,4,5 @ TJ =25°C
Ipp=4.5A, tp = 8/20 us
VR = 0V, f = 1MHz, between I/O pins
VR = 0V, f = 1MHz, any I/O pin to ground
SYMBOL
VRWM
IRM
VBR
VF
Vc
CJ
SLP2510P8
SLP2510P8
DIM. MIN.
MAX.
A 0.45
A1 0.00
0.55
0.05
A3 0.152 REF.
D 2.45 2.55
E 0.95 1.05
D1 0.35
0.45
E1 0.35
0.45
b 0.15 0.25
e 0.50 BSC
L 0.35 0.45
All dimension in millimeter
PIN ASSIGNMENT
1,2,4,5
Input lines
6,7,9,10
NC
3,8 Ground
VALUE
50
4.5
-55 to +125
55 to +150
260
UNIT
W
A
°C
°C
°C
MIN
TYP.
MAX
UNIT
-- -- 5.0 V
-- -- 1.0 uA
6.0 -- -- V
--
0.85
1.1 V
-- -- 10 V
-- 0.3 0.4
pF
-- --
0.8
REV. 4, SEP-2014, KSIR33

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RATING AND CHARACTERISTIC CURVES
L05ESDL5V0NA-4
Figure 1. 8/20 us pulse waveform
according to IEC 61000-4-5
1000
100
TJ =25°C, tp (us) = 8/20 us
exponentially decay waveform
10
1
1 10 100 1000
Pulse Time (us)
Figure 3. Power Dissipation versus Pulse Time
2
Any I/O pin to ground
1
TJ =25°C, f=1MHz, Vosc=100mV
0
01 23 45
Reverse Voltage (V)
Figure 5. Typical Junction Capacitance
Figure 2. ESD pulse waveform
according to IEC 61000-4-2
1.2
0.8
0.4
0
0 25 50 75 100 125 150
Junction Temperature ( )
Figure 4. Peak pulse power versus TJ
1000.0
100.0
10.0
1.0
0.1
0
25 50 75 100
Junction Temperature ( )
125
Figure 6. Reverse Leakage Current versus TJ

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RATING AND CHARACTERISTIC CURVES
L05ESDL5V0NA-4
I/O1
+/-8KV
ESD Contact
discharge
V (i/o)
Figure 7. ESD Test Configuration
Figure 8. Clamped +8 kV ESD voltage waveform
Figure 9. Clamped -8 kV ESD voltage waveform

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APPLICATION INFORMATION
L05ESDL5V0NA-4
DisplayPort
Connector
I/O 1 1 .. .. ..10 NC
I/O 2 2 .. .. .. 9 NC
GND 3
8 GND
I/O 3 NC
4 .. .. .. 7
I/O 4 5 .. .. .. 6 NC
L05ESDL5V0NA-4
I/O 1 1 .. .. ..10 NC
I/O 2 2 .. .. .. 9 NC
GND 3
8 GND
I/O 3 4 .. .. .. 7 NC
I/O 4 5 .. .. .. 6 NC
L05ESDL5V0NA-4
Figure 12. Display Port ESD Protection
ML Lane0 +
ML Lane0 -
ML Lane1 +
ML Lane1 -
ML Lane2 +
ML Lane2 -
ML Lane3 +
ML Lane3 -
MDDI Data0+
MDDI Data0-
MDDI Link
Controller
( HOST )
MDDI Data1+
MDDI Data1-
MDDI Stb+
MDDI Stb-
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L05ESDL5V0NA-4
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L05ESDL5V0NA-4
MDDI Data0+
MDDI Data0-
MDDI Data1+
MDDI Data1-
MDDI Stb+
MDDI Stb-
MDDI Link
Controller
( Client )
Figure 13. MDDI Interface ESD Protection

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APPLICATION INFORMATION
L05ESDL5V0NA-4
LVDS
Data
Input
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L05ESDL5V0NA-4
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L05ESDL5V0NA-4
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
LVDS
Data
Output
OUT4+
OUT4-
Figure 14. LVDS Interface ESD Protection
A+
SATA
A-
Connector B+
B-
I/O 1
I/O 2
GND
I/O 3
I/O 4
1 .. .. ..10
2 .. .. .. 9
38
4 .. .. .. 7
5 .. .. .. 6
NC
NC
GND
NC
NC
L05ESDL5V0NA-4
A+
A-
STAT
B+ Controller
B-
Figure 15. Serial ATA ESD Protection