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MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408A is a 4,194,304-bit CMOS Static RAM organizedas
524,288-word by 8-bit. This device is fabricated usingMitsubishi's
high-performance silicon-gate CMOS technology.This state-of-the-art
process technology, combined withinnovative circuit design
techniques, yields high-density and low-power devices. The
M5M5408A is suitable for memoryapplications where high reliability,
large storage, simpleinterfacing and battery back-up are important
design objectives.
The M5M5408A is available in 32-pin plastic SOP(M5M5408AFP) ,
32-pin plastic normal-lead-bend TSOP(M5M5408ATP) and 32-pin
plastic reverse-lead-bend TSOP(M5M5408ART) packages. Two
types of TSOP's are suitable forSurface Mounting on double-sided
printed circuit boards.
FEATURES
Type name
M5M5408AFP, TP, RT -55L
M5M5408AFP, TP, RT -70L
M5M5408AFP, TP, RT -10L
M5M5408AFP, TP, RT -55LL
M5M5408AFP, TP, RT -70LL
M5M5408AFP, TP, RT -10LL
Access
time
(max.)
55ns
70ns
100ns
55ns
70ns
100ns
Power supply current
Active Stand-by
(max.)
(max.)
100µA
30mA (Vcc=5.5V*)
(1MHz)
20µA
30mA (Vcc=5.5V*)
(1MHz)
0.4µA
(Vcc=3V**)
* at 70°C / **at 25°C
• Single +5V power supply
• No clocks, No refresh
• All inputs and outputs are TTL compatible.
• Easy memory expansion and power down by S
• Data retention supply voltage=2.0V to 5.5V
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Common Data I/O
• Battery backup capability
• Small stand-by current…………0.4µA (typical)
• Package
M5M5408AFP : 32 pin 525 mil SOP
M5M5408ATP : 32 pin 400 mil TSOP(II)
M5M5408ART : 32 pin 400 mil TSOP(II)
APPLICATION
Small capacity memory units
IC card
Battery operating system
PIN CONFIGURATION (TOP VIEW)
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ1 13
DQ2 14
DQ3 15
(0V)GND 16
32 VCC(5V)
31 A15
30 A17
29 W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 S
21 DQ8
20 DQ7
19 DQ6
18 DQ5
17 DQ4
Outline32P2M-A (AFP)
32P3Y-H (ATP)
(5V)VCC
A15
A17
W
A13
A8
A9
A11
OE
A10
S
DQ8
DQ7
DQ6
DQ5
DQ4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1 A18
2 A16
3 A14
4 A12
5 A7
6 A6
7 A5
8 A4
9 A3
10 A2
11 A1
12 A0
13 DQ1
14 DQ2
15 DQ3
16 GND(0V)
Outline32P3Y-J (ART)
PIN DISCRIPTION
A0 ..... A18: ADDRESS INPUTS
DQ1..... DQ8: DATA INPUTS & OUTPUTS
S: CHIP SELECT INPUT
W: WRITE ENABLE INPUT
OE: OUTPUT ENABLE INPUT
Vcc: Power supply
GND: Ground
MITSUBISHI
ELECTRIC

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MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
BLOCK DIAGRAM
A7 5
A6 6
A10 23
A11 25
A9 26
A8 27
A13 28
A17 30
A15 31
524288 WORDS
x 8 BITS
512 ROWS
x 128 COLUMNS
x 64 BLOCKS
13 DQ1
14 DQ2
15 DQ3
17 DQ4
18 DQ5
19 DQ6
20 DQ7
21 DQ8
A18 1
A16 2
A14 3
A12 4
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
CLOCK
GENERATOR
29 W
22 S
24 OE
32 VCC
(5V)
16 GND
(0V)
FUNCTION
The operation mode of the M5M5408A is determined by
acombination of the device control inputs S, Wand OE.Each
mode is summarized in the truth table.
A write cycle is executed whenever the low level Woverlaps
with the low level S. The address must be set upbefore the
write cycle and must be stable during the entirecycle. The data
is latched into a cell on the trailing edge of Wor S, whichever
occurs first, requiring the set-up and holdtime relative to these
edge to be maintained. The outputenable OE directly controls
the output stage. Setting theOE at a high level, the output
stage is in a high-impedancestate, and the data bus contention
problem in the write cycleis eliminated.
A read cycle is executed by setting W at a high level andOEat
a low level while S are in an active state(S=L).
When setting S at a high level, the chips are in a
non-selectable mode in which both reading and writing are
disabled.In this mode, the output stage is in a high-impedance
state,allowing OR-tie with other chips and memory expansion
by S.The power supply current is reduced as low as the
stand-bycurrent which is specified as Icc3 or Icc4, and the
memorydata can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation
inthe non-selected mode.
TRUTH TABLE
S W OE
Mode
H X X Non selection
LLX
Write
L HL
Read
L HH
Read
DQ
High-impedance
Data input
Data output
High-impedance
Icc
Stand-by
Active
Active
Active
MITSUBISHI
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MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
Vi
Vo
Pd
Topr
Tstg
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
* -3.0V in case of AC ( Pulse width 50ns)
Conditions
With respect to GND
Ta=25°C
Ratings
- 0.3 ~ 7
- 0.3* ~ Vcc + 0.3
0 ~ Vcc
700
0 ~ 70
-65 ~ 150
Unit
V
V
V
mW
°C
°C
DC ELECTRICAL CHARACTERISTICS (Ta=0 - 70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
Test Conditions
Limits
Min. Typ. Max.
VIH
VIL
VOH
VOL
Ii
Io
Icc1
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Active supply current (AC, MOS-lvel)
IOH= - 1mA
IOH= - 0.1mA
IOL = 2 mA
Inputs = 0 ~ Vcc
S = VIH
OE= VIH, DQ=0 ~ Vcc
S 0.2
Other inputs 0.2V or Vcc-0.2V
DQ = open (duty 100%)
2.2
-0.3*
2.4
Vcc-0.5
minimum
cycle
1MHz
S = VIL
Icc2 Active supply current (AC, TTL-level) Other inputs = VIH or VIL
DQ = open (duty 100%)
minimum
cycle
1MHz
Icc3 Stand-by current
Icc4 Stand-by current
-L
S Vcc - 0.2V,
version
Other inputs = 0 ~ Vcc
-LL
version
S = VIH, other inputs=0 ~ Vcc
Vcc+0.3
0.8
0.4
±1
±1
50 80
25 30
60 90
30 40
100
1 20
3
Unit
V
V
V
V
V
µA
µA
mA
mA
mA
mA
µA
µA
mA
* -3.0V in case of AC ( Pulse width 50ns)
CAPACITANCE (Ta=0 - 70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
Ci Input capacitance
Co Output capacitance
Test Conditions
Min.
Vi = GND, Vi = 25mV rms, f = 1MHz
Vo = GND, Vo = 25mV rms, f = 1MHz
Note1. Direction for current flowing into IC is indicated as positive value.
2. Typical value is for Ta=25°C and Vcc=5.0V
3. Ci and Co are random samples ,not production tested.
Limits
Typ. Max.
6
8
Unit
pF
pF
MITSUBISHI
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MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=0 - 70°C, Vcc=5V±10%, unless otherwise noted)
(1) MEASUREMENT CONDITIONS
Input pulse …………………VIH=2.4V, VIL=0.6V(AFP,TP,RT-70L,-10L,-70LL,-10LL)
VIH=3.0V, VIL=0V(AFP,TP,RT-55L,-55LL)
Input rise and fall time ……5ns
Output reference level ……VOH=VOL=1.5V
For ten and tdis, transition is measured ±500mV
from steady state voltage
Output loads Show in Fig. 1;
CL=100pF(AFP,TP,RT-70L,-10L,-70LL,-10LL)
CL=30pF(AFP,TP,RT-55L,-55LL)
CL=5pF (for ten,tdis)
(2) READ CYCLE
Vcc
1.8k
DQ
990C L
CL Includes jig and scope capacitance
Fig.1 Output load
Symbol
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tv(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address change
M5M5408AFP,TP,RT
Limits
M5M5408AFP,TP,RT
M5M5408AFP,TP,RT
-55L, -55LL
-70L, -70LL
-10L, -10LL
Min. Max. Min. Max. Min. Max.
55 70 100
55 70 100
55 70 100
25 35 50
20 25 35
20 25 35
10 10 10
555
10 10 10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
M5M5408AFP,TP,RT
-55L, -55LL
Limits
M5M5408AFP,TP,RT
-70L, -70LL
M5M5408AFP,TP,RT
-10L, -10LL
Min. Max. Min. Max. Min. Max.
tCW Write cycle time
55 70 100
tw(W) Write pulse width
40 50 60
tsu(A) Address set up time
000
tsu(A-WH) Address set up time with respect to W high 50 60 80
tsu(S) Chip select set up time
50 60 80
tsu(D) Data set up time
25 30 35
th(D) Data hold time
000
trec(W) Write recovery time
000
tdis(W) Output disable time after W low
20 25 35
tdis(OE) Output disable time after OE high
20 25 35
ten(W) Output enable time after W high
5
5
5
ten(OE) Output enable time after OE low
5
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI
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MITSUBISHI LSIs
M5M5408AFP,TP,RT-55L, -70L,-10L
-55LL,-70LL,-10LL
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
A0 ~ A18
S
OE
DQ1 ~ DQ8
(Dout)
( Note 4)
( Note 4)
tCR
ta(A)
ta(S)
ta(OE)
ten(OE)
ten(S)
tv(A)
tdis(S)
tdis(OE)
DATA valid
( Note 4)
( Note 4)
Write cycle ( WE control mode )
A0 ~ A18
S
OE
W
DQ1 ~ DQ8
(Din)
DQ1 ~ DQ8
(Dout)
( Note 4)
tCW
tsu(S)
tsu(A-WH)
tsu(A)
tdis(W)
tdis(OE)
tw(W)
trec(W)
tsu(D)
th(D)
DATA valid
ten(OE)
ten(W)
( Note 4)
MITSUBISHI
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