AT91RM3400.pdf 데이터시트 (총 19 페이지) - 파일 다운로드 AT91RM3400 데이타시트 다운로드

No Preview Available !

Features
Industry-standard Architecture
12ns Maximum Pin-to-pin Delay
Zero Power – 100µA Maximum Standby Power (Input Transition Detection)
CMOS and TTL Compatible Inputs and Outputs
Advanced Electrically ErasableTechnology
– Reprogrammable
– 100% Tested
Latch Feature Holds Inputs to Previous Logic State
High-reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200mA Latchup Immunity
Industrial Temperature Ranges
Dual-in-line and Surface Mount Standard Pinouts
PCI Compliant
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
High-performance
Electrically
Erasable
Programmable
Logic Device
1. Description
The Atmel® ATF22V10CZ/CQZ is a high-performance CMOS (electrically erasable)
programmable logic device (PLD) which utilizes The Atmel proven electrically eras-
able Flash memory technology. Speeds down to 12ns with zero standby power
dissipation are offered. All speed ranges are specified over the full 5V ±10% range for
industrial temperature ranges; 5V ±5% for commercial range 5-volt devices. The
ATF22V10CZ/CQZ provides a low voltage and edge-sensing “zero” power CMOS
PLD solution with “zero” standby power (5µA typical). The ATF22V10CZ/CQZ pro-
vides a “zero” power CMOS PLD solution with 5V operating voltages, powering down
automatically to the zero power-mode through The Atmel patented Input Transition
Detection (ITD) circuitry when the device is idle, offering “zero” (100µA worst case)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability. Pin “keeper” circuits on input
and output pins eliminate static power consumed by pull-up resistors. The “CQZ” com-
bines the low high-frequency ICC of the “Q” design with the “Z” feature.
The ATF22V10CZ/CQZ incorporates a superset of the generic architectures, which
allows direct replacement of the 22V10 family and most 24-pin combinatorial PLDs.
Ten outputs are each allocated 8 to 16 product terms. Three different modes of opera-
tion, configured automatically with software, allow highly complex logic functions to be
realized.
Atmel ATF22V10CZ
Atmel ATF22V10CQZ
ATF22V10CZ is
Not Recommended for New
Design. Replaced by
ATF22V10CQZ.
0778L–PLD–8/10

No Preview Available !

Figure 1-1. Block Diagram
2. Pin Configurations
Table 2-1. Pin Configurations (All Pinouts Top View)
Pin Name
CLK
IN
I/O
VCC
Function
Clock
Logic Inputs
Bi-directional Buffers
+5V Supply
Figure 2-1. TSSOP
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
Figure 2-3. PLCC
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
Figure 2-2. DIP/SOIC
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
IN
IN
IN
GND*
IN
IN
IN
5
6
7
8
9
10
11
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
Note:
For PLCC, P1, P8, P15 and P22 can be
left unconnected. For superior perfor-
mance, connect VCC to pin 1 and GND
to 8, 15, and 22
2 Atmel ATF22V10C(Q)Z
0778L–PLD–8/10

No Preview Available !

Atmel ATF22V10C(Q)Z
3. Absolute Maximum Ratings*
Temperature Under Bias .................. -40°C to +85°C
Storage Temperature...................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground...........................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming......................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground.........................-2.0V to +14.0V(1)
*NOTICE:
Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V DC, which may undershoot to -
2.0V for pulses of less than 20ns. Maximum output pin volt-
age is VCC + 0.75V DC, which may overshoot to 7.0V for
pulses of less than 20ns.
4. DC and AC Operating Conditions
Operating Temperature (Ambient)
VCC Power Supply
Commercial
0C - 70C
5V± 5%
Industrial
-40C - 85C
5V± 10%
4.1 DC Characteristics
Symbol
Parameter
Condition
Min Typ
Max
IIL
Input or I/O Low
Leakage Current
0 VIN VIL (Max)
IIH
Input or I/O High
Leakage Current
3.5 VIN VCC
-10
10
ICC
Clocked Power
Supply Current
VCC = Max
Outputs Open,
f = 15MHz
CZ-12, 15
CZ-15
CQZ-20
CQZ-20
Com
Ind
Com
Ind
90 150
90 180
40 60
40 80
CZ-12, 15 Com
ISB
Power Supply Current,
Standby
VCC = Max
VIN = MAX
Outputs Open
CZ-15
CQZ-20
Ind
Com
CQZ-20
Ind
5 100
5 120
5 100
5 120
IOS(1)
Output Short Circuit
Current
VOUT = 0.5V
-130
VIL
VIH
VOL
VOH
Note:
Input Low Voltage
-0.5 0.8
Input High Voltage
2.0 VCC + 0.75
Output Low Voltage
VIN = VIH or VIL
VCC = Min,
IOL = 16mA
0.5
Output High Voltage
VIN = VIH or VIL
VCCIO = Min,
IOH = -4.0mA
2.4
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec
Units
µA
µA
mA
mA
mA
mA
µA
µA
µA
µA
mA
V
V
V
V
0778L–PLD–8/10
3

No Preview Available !

4.2 AC Waveforms
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
CP
ASYNCH. RESET
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
tS tH
tW
tW
tP
tAW tAR
tCO tAP
tER tEA
VALID
VALID
OUTPUT
DISABLED
VALID
tPD tER tEA
VALID
VALID
OUTPUT
DISABLED
VALID
4.3 AC Characteristics(1)
-12
Symbol Parameter
Min Max
tPD
Input or Feedback to Non-registered Output
3
12
tCF Clock to Feedback
6
tCO Clock to Output
28
tS Input or Feedback Setup Time
10
tH Input Hold Time
0
tW Clock Width
6
External Feedback 1/(tS + tCO)
fMAX Internal Feedback 1/(tS + tCF)
No Feedback 1/(tP)
55.5
62
83.3
tEA Input to Output Enable - Product Term
3 12
tER Input to Output Disable - Product Term
2 15
tPZX OE Pin to Output Enable
2 12
tPXZ OE Pin to Output Disable
2 15
tAP
Input or I/O to Asynchronous Reset of
Register
3 10
tSP Setup Time, Synchronous Preset
tAW Asynchronous Reset Width
tAR Asynchronous Reset Recovery Time
tSPR
Synchronous Preset to Clock Recovery
Time
10
7
5
10
Note: 1. See ordering information for valid part numbers
-15
Min Max
3 15
4.5
28
10
0
6
55.5
69
83.3
3 15
3 15
2 15
2 15
3 15
10
8
6
10
-20
Min Max
3 20
8
2 12
14
0
10
38.5
45.5
50.0
3 20
3 20
2 20
2 20
3 22
14
20
20
14
Units
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 Atmel ATF22V10C(Q)Z
0778L–PLD–8/10

No Preview Available !

4.4 Input Test Waveforms
4.4.1 Input Test Waveforms and Measurement Levels
Atmel ATF22V10C(Q)Z
4.4.2 Output Test Loads
Note:
Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’
delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification
conditions.
4.5 Pin Capacitance
Table 4-1. Pin Capacitance (f = 1MHz, T = 25C(1)
CIN
CI/O
Note:
Typ Max
Units
Conditions
8 10
pF
VIN = 0V; f = 1.0MHz
8 10
pF
VOUT = 0V; f = 1.0MHz
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested
4.6 Power-up Reset
The registers in the Atmel® ATF22V10CZ/CQZ are designed to reset during power-up. At a point delayed slightly
from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic and start below 0.7V
2. The clock must remain stable during TPR
3. After TPR occurs, all input and feedback setup times must be met before driving the clock pin high
4.7 Preload of Register Outputs
The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
0778L–PLD–8/10
5