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Features
Incorporates the ARM920TARM® Thumb® Processor
– 200 MIPS at 180 MHz, Memory Management Unit
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– In-circuit Emulator including Debug Communication Channel
– Mid-level Implementation Embedded Trace Macrocell(256-ball BGA Package
only)
Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode
Additional Embedded Memories
– 16K Bytes of SRAM and 128K Bytes of ROM
External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to
CompactFlash® and NAND Flash/SmartMedia®
System Peripherals for Enhanced Performance:
– Enhanced Clock Generator and Power Management Controller
– Two On-chip Oscillators with Two PLLs
– Very Slow Clock Operating Mode and Software Power Optimization Capabilities
– Four Programmable External Clock Signals
– System Timer Including Periodic Interrupt, Watchdog and Second Counter
– Real-time Clock with Alarm Interrupt
– Debug Unit, Two-wire UART and Support for Debug Communication Channel
– Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored
Interrupt Sources, Spurious Interrupt Protected
– Seven External Interrupt Sources and One Fast Interrupt Source
– Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change
Interrupt and Open-drain Capability on Each Line
– 20-channel Peripheral DMA Controller (PDC)
Ethernet MAC 10/100 Base-T
– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
– Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
– Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package)
– Integrated FIFOs and Dedicated DMA Channels
USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Multimedia Card Interface (MCI)
– Automatic Protocol Control and Fast Automatic Data Transfers
– MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards
Three Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I2S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Support for ISO7816 T0/T1 Smart Card
– Hardware Handshaking
– RS485 Support, IrDA® Up To 115 Kbps
– Full Modem Control Lines on USART1
Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects
ARM920T-based
Microcontroller
AT91RM9200
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
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Two 3-channel, 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
Two-wire Interface (TWI)
– Master Mode Support, All 2-wire Atmel EEPROMs Supported
IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
Power Supplies
– 1.65V to 1.95V for VDDCORE, VDDOSC and VDDPLL
– 3.0V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)
Available in a 208-pin Green PQFP or 256-ball RoHS-compliant BGA Package
1. Description
The AT91RM9200 is a complete system-on-chip built around the ARM920T ARM Thumb pro-
cessor. It incorporates a rich set of system and application peripherals and standard interfaces
in order to provide a single-chip solution for a wide range of compute-intensive applications that
require maximum functionality at minimum power consumption at lowest cost.
The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a low-latency
External Bus Interface (EBI) for seamless connection to whatever configuration of off-chip mem-
ories and memory-mapped peripherals is required by the application. The EBI incorporates
controllers for synchronous DRAM (SDRAM), Burst Flash and Static memories and features
specific circuitry facilitating the interface for NAND Flash/SmartMedia and Compact Flash.
The Advanced Interrupt Controller (AIC) enhances the interrupt handling performance of the
ARM920T processor by providing multiple vectored, prioritized interrupt sources and reducing
the time taken to transfer to an interrupt handler.
The Peripheral DMA Controller (PDC) provides DMA channels for all the serial peripherals,
enabling them to transfer data to or from on- and off-chip memories without processor interven-
tion. This reduces the processor overhead when dealing with transfers of continuous data
streams.The AT91RM9200 benefits from a new generation of PDC which includes dual pointers
that simplify significantly buffer chaining.
The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines with general-
purpose data I/Os for maximum flexibility in device configuration. An input change interrupt,
open drain capability and programmable pull-up resistor is included on each line.
The Power Management Controller (PMC) keeps system power consumption to a minimum by
selectively enabling/disabling the processor and various peripherals under software control. It
uses an enhanced clock generator to provide a selection of clock signals including a slow clock
(32 kHz) to optimize power consumption and performance at all times.
The AT91RM9200 integrates a wide range of standard interfaces including USB 2.0 Full Speed
Host and Device and Ethernet 10/100 Base-T Media Access Controller (MAC), which provides
connection to a extensive range of external peripheral devices and a widely used networking
layer. In addition, it provides an extensive set of peripherals that operate in accordance with sev-
eral industry standards, such as those used in audio, telecom, Flash Card, infrared and Smart
Card applications.
To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug
features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real
time trace. This enables the development and debug of all applications, especially those with
real-time constraints.
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2. Block Diagram
Bold arrows (
) indicate master-to-slave dependency.
Figure 2-1. AT91RM9200 Block Diagram
TST0-TST1
NRST
JTAGSEL
TDI
TDO
TMS
TCK
NTRST
Reset
and
Test
JTAG
Scan
ARM920T Core
ICE
ETM
Instruction Cache
16K bytes
MMU
Data Cache
16K bytes
FIQ
IRQ0-IRQ6
PCK0-PCK3
PLLRCB
PLLRCA
XIN
XOUT
XIN32
XOUT32
DRXD
DTXD
PLLB
PLLA
OSC
OSC
AIC
PMC
System
Timer
RTC
DBGU
PDC
Fast SRAM
16K bytes
Fast ROM
128K bytes
Peripheral
Bridge
Peripheral
DMA
Controller
Address
Decoder
Abort
Status
Misalignment
Detector
Bus
Arbiter
Memory
Controller
EBI
CompactFlash
NAND Flash
SmartMedia
SDRAM
Controller
Burst
Flash
Controller
Static
Memory
Controller
DDM
DDP
MCCK
MCCDA
MCDA0-MCDA3
MCCDB
MCDB0-MCDB3
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
DSR1
DTR1
DCD1
RI1
RXD2
TXD2
SCK2
RTS2
CTS2
RXD3
TXD3
SCK3
RTS3
CTS3
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
TWD
TWCK
PIOA/PIOB/PIOC/PIOD
Controller
FIFO
USB Device
MCI
PDC
USART0
PDC
USART1
PDC
USART2
PDC
USART3
PDC
SPI
PDC
TWI
APB
DMA
FIFO
USB Host
DMA
FIFO
Ethernet MAC 10/100
PDC
SSC0
PDC
SSC1
PDC
SSC2
Timer Counter
TC0
TC1
TC2
Timer Counter
TC3
TC4
TC5
AT91RM9200
TSYNC
TCLK
TPS0 - TPS2
TPK0 - TPK15
BMS
D0-D15
A0/NBS0
A1/NBS2/NWR2
A2-A15/A18-A22
A16/BA0
A17/BA1
NCS0/BFCS
NCS1/SDCS
NCS2
NCS3/SMCS
NRD/NOE/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK
SDCKE
RAS-CAS
SDWE
SDA10
BFRDY/SMOE
BFCK
BFAVD
BFBAA/SMWE
BFOE
BFWE
A23-A24
A25/CFRNW
NWAIT
NCS4/CFCS
NCS5/CFCE1
NCS6/CFCE2
NCS7
D16-D31
HDMA
HDPA
HDMB
HDPB
ETXCK-ERXCK-EREFCK
ETXEN-ETXER
ECRS-ECOL
ERXER-ERXDV
ERX0-ERX3
ETX0-ETX3
EMDC
EMDIO
EF100
TF0
TK0
TD0
RD0
RK0
RF0
TF1
TK1
TD1
RD1
RK1
RF1
TF2
TK2
TD2
RD2
RK2
RF2
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
TCLK3
TCLK4
TCLK5
TIOA3
TIOB3
TIOA4
TIOB4
TIOA5
TIOB5
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3. Signal Description
Table 3-1. Signal Description by Peripheral
Pin Name
VDDIOM
VDDIOP
VDDPLL
VDDCORE
VDDOSC
GND
GNDPLL
GNDOSC
XIN
XOUT
XIN32
XOUT32
PLLRCA
PLLRCB
PCK0 - PCK3
TCK
TDI
TDO
TMS
NTRST
JTAGSEL
TSYNC
TCLK
TPS0 - TPS2
TPK0 - TPK15
NRST
TST0 - TST1
Function
Type
Power
Memory I/O Lines Power Supply
Power
Peripheral I/O Lines Power Supply
Power
Oscillator and PLL Power Supply
Power
Core Chip Power Supply
Power
Oscillator Power Supply
Power
Ground
Ground
PLL Ground
Ground
Oscillator Ground
Ground
Clocks, Oscillators and PLLs
Main Crystal Input
Input
Main Crystal Output
Output
32KHz Crystal Input
Input
32KHz Crystal Output
Output
PLL A Filter
Input
PLL B Filter
Input
Programmable Clock Output
Output
ICE and JTAG
Test Clock
Input
Test Data In
Input
Test Data Out
Output
Test Mode Select
Input
Test Reset Signal
Input
JTAG Selection
Input
ETM
Trace Synchronization Signal
Output
Trace Clock
Output
Trace ARM Pipeline Status
Output
Trace Packet Port
Output
Reset/Test
Microcontroller Reset
Input
Test Mode Select
Input
Active
Level Comments
3.0V to 3.6V
3.0V to 3.6V
1.65V to 1.95V
1.65V to 1.95V
1.65V to 1.95V
Schmitt trigger
Internal Pull-up, Schmitt trigger
Tri-state
Internal Pull-up, Schmitt trigger
Low Internal Pull-up, Schmitt trigger
Schmitt trigger
Low No on-chip pull-up, Schmitt trigger
Must be tied low for normal
operation, Schmitt trigger
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AT91RM9200
Table 3-1. Signal Description by Peripheral
Pin Name
BMS
DRXD
DTXD
IRQ0 - IRQ6
FIQ
PA0 - PA31
PB0 - PB29
PC0 - PC31
PD0 - PD27
D0 - D31
A0 - A25
NCS0 - NCS7
NWR0 - NWR3
NOE
NRD
NUB
NLB
NWE
NWAIT
NBS0 - NBS3
CFCE1 - CFCE2
CFOE
CFWE
CFIOR
CFIOW
CFRNW
CFCS
Function
Type
Memory Controller
Boot Mode Select
Input
Debug Unit
Debug Receive Data
Input
Debug Transmit Data
Output
AIC
External Interrupt Inputs
Input
Fast Interrupt Input
Input
PIO
Parallel IO Controller A
I/O
Parallel IO Controller B
I/O
Parallel IO Controller C
I/O
Parallel IO Controller D
I/O
EBI
Data Bus
I/O
Address Bus
Output
SMC
Chip Select Lines
Output
Write Signal
Output
Output Enable
Output
Read Signal
Output
Upper Byte Select
Output
Lower Byte Select
Output
Write Enable
Output
Wait Signal
Input
Byte Mask Signal
Output
EBI for CompactFlash Support
CompactFlash Chip Enable
Output
CompactFlash Output Enable
Output
CompactFlash Write Enable
Output
CompactFlash IO Read
Output
CompactFlash IO Write
Output
CompactFlash Read Not Write
Output
CompactFlash Chip Select
Output
Active
Level Comments
Debug Receive Data
Debug Transmit Data
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
Pulled-up input at reset
0 at reset
Low 1 at reset
Low 1 at reset
Low 1 at reset
Low 1 at reset
Low 1 at reset
Low 1 at reset
Low 1 at reset
Low
Low 1 at reset
Low
Low
Low
Low
Low
Low
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