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DATASHEET
ISL6262
Two-Phase Core Regulator for IMVP-6 Mobile CPUs
The ISL6262 is a two-phase buck converter regulator
implementing Intel® IMVP-6 protocol, with embedded gate
drivers. The two-phase buck converter uses two interleaved
channels to effectively double the output voltage ripple
frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
The heart of the ISL6262 is R3 Technology™, Intersil’s
Robust Ripple Regulator modulator. Compared with the
traditional multiphase buck regulator, the R3 Technology™
has the fastest transient response. This is due to the R3
modulator commanding variable switching frequency during
a load transient.
Intel Mobile Voltage Positioning (IMVP) is a smart voltage
regulation technology, which effectively reduces power
dissipation in Intel Pentium processors. To boost battery life,
the ISL6262 supports DPRSLRVR (deeper sleep),
DPRSTP# and PSI# functions and maximizes the efficiency
via automatically enabling different phase operation modes.
At heavy load operation of the active mode, the regulator
commands the two phase continuous conduction mode
(CCM) operation. While the PSI# is asserted at the medium
load in the active mode, the ISL6262 smoothly disables one
phase and operates in a one-phase CCM. When the CPU
enters deeper sleep mode, the ISL6262 enables diode
emulation to maximize the efficiency at the light load.
A 7-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
A 0.5% system accuracy of the core output voltage over
temperature is achieved by the ISL6262.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately measured and regulated per Intel IMVP-6
specifications. Current sensing can be realized using either
lossless inductor DCR sensing or precision resistor sensing.
A single NTC thermistor network thermally compensates the
gain and the time constant of the DCR variations.
FN9199
Rev 2.00
May 15, 2006
Features
• Precision Two-phase CORE Voltage Regulator
- 0.5% System Accuracy Over Temperature
- Enhanced Load Line Accuracy
• Internal Gate Driver with 2A Driving Capability
• Dynamic Phase Adding/Dropping
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Support VID Change on-the-fly
• Multiple Current Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Thermal Monitor
• User Programmable Switching Frequency
• Differential Remote CPU Die Voltage Sensing
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
PART
TEMP.
MARKING (°C)
PKG.
PACKAGE DWG. #
ISL6262CRZ ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262CRZ-T ISL6262CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
ISL6262IRZ
(Note)
ISL6262IRZ -40 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL6262IRZ-T ISL6262IRZ -40 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN9199 Rev 2.00
May 15, 2006
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ISL6262
Pinout
ISL6262 (7x7 QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
PGOOD 1
PSI# 2
PGD_IN 3
RBIAS 4
VR_TT# 5
NTC 6
SOFT 7
OCSET 8
VW 9
COMP 10
FB 11
FB2 12
GND PAD
(BOTTOM)
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
FN9199 Rev 2.00
May 15, 2006
Page 2 of 27

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ISL6262
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . . -0.3 -+7V
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . -10°C to 100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to 125°C
Ambient Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 100°C
Junction Temperature, Industrial . . . . . . . . . . . . . . . -40°C to 125°C
Thermal Information
Thermal Resistance (Typical)
JA°C/W JC°C/W
QFN Package (Notes 1, 2). . . . . . . . . .
29
4.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 3.3V
VR_ON = 0V
+3.3V Supply Current
Battery Supply Current at VIN pin
POR (Power-On Reset) Threshold
SYSTEM AND REFERENCES
I3V3
IVIN
PORr
PORf
No load on CLK_EN#
VR_ON = 0V, VIN = 25V,
VDD Rising
VDD Falling
System Accuracy
%Error
(Vcc_core)
ISL6262CRZ
No load, closed loop, active mode,
TA = 0°C to 100°C, VID = 0.75-1.5V
VID = 0.5-0.7375V
VID = 0.3-0.4875V
%Error
(Vcc_core)
ISL6262IRZ
TA = -40°C to 100°C, VID = 0.75-1.5V
VID = 0.5-0.7375V
VID = 0.3-0.4875V
RBIAS Voltage
Boot Voltage
Maximum Output Voltage
RRBIAS
VBOOT
VCC_CORE
(max)
RRBIAS = 147k
VID = [0000000]
VCC_CORE
(min)
VID = [1100000]
VID Off State
VID = [1111111]
CHANNEL FREQUENCY
Nominal Channel Frequency
Adjustment Range
fSW RFSET = 3.9k, 2 channel operation,
Vcomp = 2V
MIN TYP MAX UNITS
- 3.1 3.6 mA
- - 1 µA
- - 1 µA
- - 1 µA
- 4.35 4.5 V
3.9 4.1
-V
-0.5 - 0.5 %
-8 - 8 mV
-15 - 15 mV
-0.8 - 0.8 %
-10 - 10 mV
-18 - 18 mV
1.45 1.47 1.49 V
1.188
1.2
1.212
V
- 1.5 - V
- 0.3 - V
- 0 -V
- 300 - kHz
200 - 500 kHz
FN9199 Rev 2.00
May 15, 2006
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ISL6262
Electrical Specifications VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
AMPLIFIERS
Droop Amplifier Offset
-0.3
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
Error Amp Slew Rate
FB Input Current
ISEN
AV0
GBW
SR
IIN(FB)
CL = 20pF
CL = 20pF
-
-
-
-
Imbalance Voltage
-
Input Bias Current
-
SOFT-START CURRENT
Soft-Start Current
Soft Geyserville Current
Soft Deeper Sleep Entry Current
Soft Deeper Sleep Exit Current
Soft Deeper Sleep Exit Current
GATE DRIVER DRIVING CAPABILITY
ISS
IGV
IC4
IC4EA
IC4EB
|SOFT - REF|>100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-47
±170
-47
35
170
UGATE Source Resistance
RSRC(UGATE) 500mA Source Current
UGATE Source Current
ISRC(UGATE) VUGATE_PHASE = 2.5V
UGATE Sink Resistance
RSNK(UGATE) 500mA Sink Current
UGATE Sink Current
ISNK(UGATE) VUGATE_PHASE = 2.5V
LGATE Source Resistance
RSRC(LGATE) 500mA Source Current
LGATE Source Current
ISRC(LGATE) VLGATE = 2.5V
LGATE Sink Resistance
RSNK(LGATE) 500mA Sink Current
LGATE Sink Current
ISNK(LGATE) VLGATE = 2.5V
UGATE to PHASE Resistance
Rp(UGATE)
GATE DRIVER SWITCHING TIMING (refer to timing diagram)
-
-
-
-
-
-
-
-
-
UGATE Turn-On Propagation Delay
tPDHU
ISL6262CRZ
TA = -10°C to 100°C
PVCC = 5V, Outputs Unloaded
20
tPDHU
ISL6262IRZ
PVCC = 5V, Outputs Unloaded
18
LGATE Turn-On Propagation Delay
tPDHL
ISL6262CRZ
TA = -10°C to 100°C
PVCC = 5V, Outputs Unloaded
7
tPDHL
ISL6262IRZ
PVCC = 5V, Outputs Unloaded
5
BOOTSTRAP DIODE
Forward Voltage
Leakage
POWER GOOD and PROTECTION MONITOR
VDDP = 5V, Forward Bias Current = 2mA
VR = 16V
0.43
-
PGOOD Low Voltage
PGOOD Leakage Current
VOL
IOH
IPGOOD = 4mA
PGOOD = 3.3V
-
-1
TYP
-
90
18
5
10
-
20
-41
±200
-41
41
200
1
2
1
2
1
2
0.5
4
1.1
30
30
15
15
0.58
-
0.11
-
MAX UNITS
0.3 mV
- dB
- MHz
- V/µs
150 nA
1 mV
- nA
-35
±230
-35
47
230
µA
µA
µA
µA
µA
1.5
-A
1.5
-A
1.5
-A
0.9
-A
- k
44 ns
44 ns
30 ns
30 ns
0.72 V
1 µA
0.4 V
1 µA
FN9199 Rev 2.00
May 15, 2006
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ISL6262
Electrical Specifications VDD = 5V, TA = -40°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
PGOOD Delay
tpgd
ISL6262CRZ
TA = -10°C to 100°C
CLK_EN# Low to PGOOD High
5.5
tpgd
ISL6262IRZ
CLK_EN# Low to PGOOD High
5.3
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OVH
OVHS
VO rising above setpoint > 1ms
VO rising above setpoint > 0.5µs
I(Rbias) = 10µA
160
1.675
9.8
OC Threshold Offset
DROOP rising above OCSET > 120µs
-3.5
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 > 1ms
-
Undervoltage Threshold
(VDIFF-SOFT)
UVf VO falling below setpoint for > 1ms
-365
LOGIC INPUTS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL
-
VR_ON, DPRSLPVR and PGD_IN
Input High
VIH
2.3
Leakage Current of VR_ON and
PGD_IN
Leakage Current of DPRSLPVR
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
IIL
IIH
IIL_DPRSLP
IIH_DPRSLP
VIL
Logic input is low
Logic input is high at 3.3V
DPRSLPVR input is low
DPRSLPVR input is high at 3.3V
-1
-
-1
-
-
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH
0.7
Leakage Current of DAC(VID0-
VID6), PSI# and DPRSTP#
THERMAL MONITOR
IIL Logic input is low
IIH Logic input is high at 1V
-1
-
NTC Source Current
NTC = 1.3 V
53
Over-Temperature Threshold
V(NTC) falling
1.165
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
RTT I = 20mA
-
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
VOH
VOL
3V3 = 3.3V, I = -4mA
ICLK_EN# = 4mA
2.9
-
TYP
6.8
6.8
200
1.7
10
-
7.5
-300
-
-
0
0
0
0.45
-
-
0
0.45
60
1.18
5
3.1
0.18
MAX
8.1
UNITS
ms
8.1 ms
240
1.725
10.2
3.5
-
-240
mV
V
µA
mV
mV
mV
1V
-V
- µA
1 µA
- µA
1 µA
0.3 V
-V
- µA
1 µA
68
1.205
9
µA
V
-V
0.4 V
FN9199 Rev 2.00
May 15, 2006
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