AN-764.pdf 데이터시트 (총 17 페이지) - 파일 다운로드 AN-764 데이타시트 다운로드

No Preview Available !

AN-764
Application Note
A FLOPPY DISK CONTROLLER USING
THE MC6852 SSDA AND OTHER M6800
MICROPROCESSOR FAMILY PARTS
Prepared by:
Larry A. Parker
Semiconductor Systems Engineering
This application note describes a floppy
disk controller based on the M6800 fam-
ily of parts. It uses the Synchronous
Serial Data Adapter (SSDA) as the primary
data interface with the MPU and does not
require DMA for transfer of data to and
from memory. A Peripheral Interface
Adapter (PIA) controls all non-date re-
lated operations in the controller (includ-
ing seek, drive selection, etc.).
MOTOROLA SelJ'Jiconducf:or Producf:s Inc.
©MOTOROLA INC., 1976

No Preview Available !

A FLOPPY DISK CONTROLLER USING THE MC6852 SSDA AND
OTHER M6800 MICROPROCESSOR FAMILY PARTS
INTRODUCTION
With the introduction of the MC6852 SSDA, the task
of interfacing synchronous serial peripherals such as
floppy disks, tape cassettes or cartridges, and bi-sync or
HDLC data channels, has been reduced significantly.
Described in this application note is an efficient and
flexible floppy disk controller design. Various features of
this design include:
• Controller operates one to four daisy-chained drives
• Four drive radial configuration possible with addi-
tional multiplexing
• Flexible drive interfacing
• MPU controls data transfer allowing:
• Store only desired data from a sector into
memory
• Search disk for pattern match without transfer-
ring data into memory until pattern is found
• Read or write entire track in one revolution;
consecutive tracks on consecutive revolutions
• DMA not required when using host MPU
• Interrupt MPU system operations on address mark
match to start operations, allowing increased
throughput
• Seek interlaced with R/W when using radial con-
figuration
• Hard or soft sectoring
• IBM or user programmable sync patterns and
format
• Write format blank disks
• Cost competitive
• Effective use of MPU leaves time available for ad-
ditional tasks (see Table 1).
• Low parts count
Controller: (MPU and RAM shared with system)
Formatter
14 TTL SSI, MSI Devices
1 SSDA
1 PIA
1 CRCCG
Data Recovery
5 TTL + filter SSI, MSI
Devices
Drive Interface
Buffers and
Receivers
5-10 TTL/CMOS Devices
+ Termination
MPU System
Interface
2-5 TTL/Three-state Devices
The disk controller system consists of four basic blocks
as shown in Figure 2. The PIA serves as the interface to
the drive controls. There are 16 available PIA lines which
allow a wide variety of drive configurations. The remain-
ing four lines are used internal to the controller. The clock
is separated from the raw disk data by the phase-locked
loop data recovery block. The SSDA has the responsibility
of synchronizing read/write operations and serializing/
deserializing the data. Error detection and system clock
functions are performed by the CRCC and clock control
logic block.
The MPU has essentially complete software control
over the system. Mechanical drive functions and status
TABLE 1
Function
Conditions
IBM Format
Microprocessor Processing
Time Available for
Non-Floppy Operations
Consecutive Processing non-floppy 1 ms between sectors
Sector RIW operations allowed
= 25 ms 21.6%
on Multiple only between sectors 11 ms at Index
Tracks
Read or
Write a
Single
Sector
Processing non-floppy
operations allowed
while RIW the sector;
a 44 /-IS RIW loop is
assumed for 2 bytes
of data
52 /-IS block available
each 192 /-IS 43.7%
42 • 52 /-IS = 2.184 ms
Consecutive
Sector R/W
on Multiple
Tracks
Processing non-floppy
operations allowed
while R/W a sector
and between sectors
as above
See above
65.3%
Search for
Sector
Assume 250 /-IS to
Read and Test 10
block for match
after Sy nc Interrupt
1.00 - 3.9 ms/rev 96.1%
Search for Assume 50 /-IS to
Track
process track info
for each step
1.00 - 50 /-lsI 99.97%
167 ms
such as step, step direction, head load, ready, write en-
able, etc. are controlled and monitored in software by the
MPU via the PIA. SSDA data transfer operations are
initialized and supervised with MPU instructions. Due to
the PIA, SSDA and system hardware configuration, pro-
gramming can be kept simple and effective with a mini-
mum of software overhead. Basic driver routines can be
Circuit diagrams e)(ternal to Motorola products are included as a means of iltulltrating typical semiconductor applications; consequently,
complete information sufficient for construction purposes is not necessarily given. The information in this Application Note has been care-
fully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information
does not convey to the purchaser of the semiconductor devices described any license under the patent rights of Motoro"; Inc. or others.
2

No Preview Available !

Timer on 1/0 Module
DC-OF
FIGURE 1 - M6800 Floppy Disc Controller Schematic
i;I DRIVE INTERFACE
~
j ~ ! !., ! i~
N
~
'j"
I
~
.l!
I
>>
>
x
a: ~
cr
N
I
'7 T
'k+5V--~~~---,----,--,
11
PE MR
CEP TC
CET
JJ J+5 J~
U~
PO
P'
P2
P3
1 1)
~. ~1417
l~ n~
~
~ 0: n~~
Y, Y2 V3
Vo
r-
Y
74153/MCl4539
~-----:.,...,.jR/W
Vcq_+5V
q~ CSO "CB2 .........
~ Cs2 ~ Cal ___ '-
+Index
Ik
+5 V -'VVV- PU
~ CS, Il. ~ PB7I4-H_I--+_--+_----------+_=:-C"'R"'C"-=:..0"---+----------------~c_+_--+----f__I----...,
V-~__~.2~~E
PB6~~~--+_--t_----------t_~+~ln~~~n~c~--1_----------------_1~+_--_t----I__+--,
.rt--~07
PB5 ..J
1rI-----j06
PBO
V1--~05
IrI-----j04
1rI-----j03
1Vr1I------~--0j012
~
CIC)
~
~
IrI-----jDO
~~---~Reset
~RSl
~RSO
PB3~-_+-I__+-----1_----~------------~-t_--t_--_t--t.
ffi'~--_I--+_--+_----------f_~I------~---+=:Sh~;f~t~C~R:..C---------J
PBO~-_+--I__+--------1_-t.
PA7~--_+--+_--t_----------t_~~-:~~--~+T~'~ac=k~0:..0------------~
PA614-___I--+_--~~--------+_~H~R~e=ad~Y~
PA5~--_+--+_--t_t_--------t_--~~------~+~:e=r:~:~~o=~~:='ed=--------------~
PA4~--_I--+_--+_+_--------+_~~~------~~~~-:~~~----~------~
PA3~--_+--+_--t_I_--------t_~~--------~+~0;~'~~t~;o~n~ln~-~0~i'~ec~ti~on~O~u~t______________~
Clk
+5V
1 .!!.j3
I.PE MR
CEP _------------_-----;;lR'
CET
f PO
Pl
P2
P3
.-------~--_ICIk
,1-
03
7416'19316
C
R
PU
n 3 5 2.2k
0.01
.F 720
'k)
1 ~6~.
2"
10·11.--12'V.2V1k~'"--"l
U MC4044
Filter
820
200
=
~,.
:31
2
VCO
6
36PF
5 7 9 '3
~MC4024
-eRC =0
+10 Sync
IrI~------l»ITm
PA2~
r--------------------------------------------t_-------------t_,
~~--~~
PA1~----~
r--" CA2
PAO~----------'
rL.C_A_'_ _ _ _V_SS~t--
~ -~R>-j) ..et 0 PU 0 __
elk a
TiJF
IiOl0 s
Switch Clock Rate
eRa
Os
0
CRO
~PsU ~PU ~P~opo0
eRa
0
elk
KQ
&BITSHIF
C ROC
0
~
7491
-VSS:IE II. VCC_ r-+5V
OO«U:-AO
I ¥~
I
L-------~~----------_+--------~-4----+_--_+_t--------~~--------t_~+_+_--_+------+_--~
~__~J".1. -----~---t-r--~~~-R-e-se-t ---r---------r-----t----r+----------r--------~+-1-+----r------r-----~
- PU
0' C£:g Al
02 A2
L----------+~~~~------+_--_1~----------------_+----~~--_t------~----+_t_------------~+~R1~~~------+__r_r1_--+_------1__1~----------_+------------_,
...03
D4 C)
05 CIC)
A3
A4
A5
I~
r- ~';»"p-u-----+----1r-----t......-'-I.--" '"-!.-./
~~ 1741o5~7-------P-U--++----------------------r__+_H...., PU
~
06 (I) A6
Jlk _I~~ :t===========~IH-I~~C:C::~~M~R;:::!·:I:~-1p~0-=1p'"'1~~P~2=~P~3=_";0" ~ h-CA7S07
tJ
:IE
RiW
cs
-I-
~
-
-
S0
r -_ _L__- -
+5/
---,-B
cs~
~ '=~: Ar----<;t:~......,~-+-t--LC_K ~O:;:O'-------~Q3T_...J R~iftf_..;~:::h::.~;;':..:~::.R:.::C:::C--I__--_I---:r---'I~B
CS 18·12
PU C R 0
'= 7476
OA G h=
__
74161/
L++---qAZ P
~ En CRe CRe
*'--_ _~I
9316 +---------t_--t_1_.......~:--_<lw" Clk
Ir.c;:-o-nt:;-;n-u-ou-,------t--1-I~-I~: :l r<J-MemoryClock
I~:- 0
~)~~~~~: ~~~~~---i-------------i----------------'gIV1r-Ir-~----::-~:=.ii20
R/W
E
«
0
... VOO );:-+5 V
CjI RS •
~r;s:;2'
I>-I--~, 07 II) CSt_-+<><
~;:~
I>-I____
II)
plu
~L-+_f-<O<
O,'ay
~ RdClk Rd Data
- Wrt Data
PU- PS INV Dout
MC8506,
pr
L=_'k-'c:;-_:J
Ju
PU
1>-I--~~~404 N iRCi r-
0503 ~ TxO~--4_------------4_----------------_+--------------------------_t--------------------------1_----t_+_~~--------r------------------------'
1D>--II-----~D-~~60012 ~~
rill1>-1__..::;0.,700 ::iii:
> - - - i5Cli
SM
TxCh
RxC~....._ r - - - - - - - - - - - - _ r - - - - - - - - - - - - - - - - - - - - - - - - « : .
Rxol---
VSSil
1 = Write
r-------------------------------~_r~ )o--______~r;;--'t-
~_!------j_r-----_t~~~--~~
°r;D»----H > - - - - 1
-Sync Latch
L-________________________________________________________________---Ic R
v~
7407
PU
12 1
lH18
8
f I~ I~ ~ I~ ~ I~ f1~on ~ ~ ls ~
VMA
::l 1:0
D7 A15 A14
~ L~
'--
1:;,. I~ ~
A7 A6A5A4
~ I=> I> li
A3 A2 A1 AO
EXORciser BUS
3
4

No Preview Available !

FIGURE 2-Floppy Disk Controller Block Diagram
To MPU
System
PIA
Drive Control
and Status
Buffers
j~
-.2.,
c
0
(J
"0
C
~'''"""
"0
"0
<{
:J
Cl.
:2
-
'----
U
IV
Line
Functions
Depend
on
Drive
Interface
~
IV
-.- 16/
/
- CRCC Status
+ Shift CRCC
R(1)/W(O)
+ Reset
0.''."",
:J
Cl.
:2
1.0 MHz Write Osc.
~
IV
Ll'
1/
SSDA
t lTxClk
Data Clock
- -RxClk
TxD
Write Data
TUF
Tx Underflow
Sync Match
SM
-RxD
Read Data
CTS r---<J
-Match
IRQ
Raw
Read
Data
-Write Data
to Drive
Buffer
Ii
PLL
Data Recovery
(5-6 TTL
MSI devices)
Clk Data
'.'I I
.-.
-.
.-.. CRCC and
Clock Control
Logic
...
-
-...
..
(1 MC8506 CRCC
Generator and
14 TTL SSI, MSI Devices)
5

No Preview Available !

written with fewer than 600 bytes of code. Operating
systems suitable to most user needs can be done within
two to four kilobytes.
Specific descriptions of the data recovery circuit and
read and write operations are discussed in the following
pages. Simplified logic diagrams are used in the circuit
descriptions. The actual system schematic is shown in
Figure l.
It is important to be familiar with the operation of the
SSDA, PIA and the IBM 3740 format in order to under-
stand the controller design. A review of the MC6820 and
MC6852 data sheets is recommended. A discussion of
drive interfacing and IBM format can be found in the
M6800 Microprocessor Applications Manual. A descrip-
tion of the software drivers and the software for the con-
troller is available upon request.
DATA RECOVERY CIRCUIT DESCRIPTION
The raw data from the drive (clock and data) is termi-
nated and buffered before clocking the first D flip-flop
(Figure 3-B and Figure 4-B). Flip-Flops 1 and 2 generate a
negative pulse 1 VCO period wide (Figure 3-D and Figure
4-D) which is used to load the reference counter with 9
and to set the data flip-flop 3.
IBM 3740 data can have only one consecutive pulse
missing in the stream. By loading the reference counter
with 9, Q3 will have a positive transition within 15 VCO
periods generating a clock edge even if the data pulse is
missing (Figure 3-E and Figure 4-E). Carryouts will occur
every 2 /1S (16/fo), nominally providing a fundamental
reference for the frequency/phase detector (Figure 3-F
and Figure 4-F). The variable input to the frequency/
phase detector is generated by dividing fo by 16, using the
carryout to give a pulse similar in duration to the
reference.
Negative transitions on Q3 are inverted and clock flip-
flop 3, whose output goes low (Figure 3-G, H and Figure
4-G, H). If a data pulse is present, the flip-flop is set by
pulse from flip-flop 2 (Figure 3-D, Figure 4-D). If no data
pulse is present, the output of flip-flop 3 remains low
until set by a data pulse which must occur within 32 /1S of
the last one. The output of flip-flop 3 is then clocked one
Q3 period later by Q3 to generate the NRZ data required
by the formatter circuitry (Figure 3-J, Figure 4-J).
The 8-bit shift register provides 16 /1S delayed data
which is fed to the CRCCG. The SSDA clocks in 8 bits of
data at 500 kHz before sync occurs and the read opera-
tion starts; because the sync data is included in the CRCC
permutation, this sync data must be included in the CRCC
field.
Phased-locked loop design is described in Motorola
Application Note AN-535.
READ OPERATION
The sync code register of the SSDA is used to synchro-
nize read operations by testing the incoming data stream,
clocked at 500 kHz (2X clock), for the first half clock and
data pattern of the desired address mark. When a match is
found, the external circuitry is released by the Sync
Match (SM) output and the second half of the address
mark (clock and data) is read from the SSDA Rx FIFO
(when it becomes available) and tested for a match with
the desired type. If it does not match the sequence is
restarted. If the second half of the address mark matches,
the desired data transfer is initiated. The external circuitry
switches the SSDA read clock to 250 kHz (1X clock) after
the second half of the address mark has been received so
that only the data portion of the remaining Rx FIFO
information is recovered. The external circuitry also con-
trols the CRCC generator (CRCCG) timing so that only
the data portion of the recovered information is clocked
into the generator.
After the data block has been transferred, the CRCC
status is made available to the MPU for 32 /1S at a PIA
peripheral line.
READ DATA LOGIC
Figure 5 is a simplified logic diagram of the read data
logic. Figure 6 is a timing diagram which shows the signal
timing relationship when a read operation is begun.
This explanation of the read data logic assumes that
system initialization has been completed. This includes
the completion of the seek and head load operation. The
enable read line is set and the formatter reset line has been
toggled to reset the sync match latch and set the switch
clock rate latch. These two previous operations are
initiated in software and are executed via the system
Peripheral Data Adapter (PIA). Initialization of the
Synchronous Serial Data Adapter, SSDA, has been com-
pleted as described in the SSDA Read Preparation section.
Raw serial data is processed by the data recovery cir-
cuit which provides the separated read data and 500 kHz
clock to the read data logic, Figure 5-A, B and Figure 6-A,
B.
The 500 kHz clock from the data recovery circuit is
inverted, delayed and then fed to the SSDA read clock
input (RxD) , via combinational AND/OR selector logic
controlled by the switch clock rate latch, Figure 5, Figure
6-C. Inverting the clock provides the correctly phased
positive transition to load the read data in the SSDA
receiver shift register. The delay (4 inverters) is necessary
to prevent a possible timing glitch which will be discussed
later. The 500 kHz, 2X clock rate will load the receiver
register with both clock and data bits from the read data
line.
When the bit pattern loaded in the receiver shift regis-
ter is equal to the pattern present in the SSDA sync code
register, the SSDA synch match output, SM, will go high
for one read clock period, Figure 6-D. When the sync
match occurs, the SSDA receive data FIFO is internally
enabled and will begin to store the read data, Figure 6-D.
6