80C86.pdf 데이터시트 (총 30 페이지) - 파일 다운로드 80C86 데이타시트 다운로드

No Preview Available !

DATASHEET
80C86
CMOS 16-Bit Microprocessor
The 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). Two modes of operation,
minimum for small systems and maximum for larger
applications such as multiprocessing, allow user
configurations to achieve the highest performance level. Full
TTL compatibility (with the exception of CLOCK) and
industry standard operation allow use of existing NMOS
8086 hardware and software designs.
Related Literature
For a full list of related documents, visit our website
80C86 product page
FN2957
Rev 5.00
Jul 13, 2018
Features
• Compatible with NMOS 8086
• Completely static CMOS design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low power operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .10mA/MHz typ
• 1MByte of direct memory addressing capability
• 24 operand addressing modes
• Bit, Byte, Word and Block Move operations
• 8-Bit and 16-Bit signed/unsigned arithmetic
- Binary, or decimal
- Multiply and divide
• Wide operating temperature range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-free available (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
CP80C86-2Z (Note 1)
CP80C86-2Z
0 to +70
40 Ld PDIP (Note 2)
(RoHS compliant)
E40.6
MD80C86-2/883
MD80C86-2/883
-55 to +125
40 Ld CERDIP
F40.6
MD80C86-2/B
MD80C86-2/B
-55 to +125
40 Ld CERDIP
F40.6
8405202QA
8405202QA
-55 to +125
40 Ld CERDIP (SMD)
F40.6
NOTES:
1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
FN2957 Rev 5.00
Jul 13, 2018
Page 1 of 39

No Preview Available !

80C86
Table of Contents
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Minimum Mode System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum Mode System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Static Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Minimum and Maximum Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I/O Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Processor RESET and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Hold Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maskable Interrupt (INTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read/Modify/Write (Semaphore) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operations Using Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
External Synchronization Using TEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Basic System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System Timing - Minimum System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus Timing - Medium Size Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Electrical Specifications – Minimum Complexity SystemAC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Electrical Specifications – Maximum Mode SystemAC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Testing Input, Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Burn-In Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Metallization Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual-In-Line Plastic Packages (PDIP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ceramic Dual-In-Line Frit Seal Packages (CERDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FN2957 Rev 5.00
Jul 13, 2018
Page 2 of 39

No Preview Available !

80C86
Functional Diagram
EXECUTION UNIT
REGISTER FILE
DATA POINTER
AND
INDEX REGS
(8 WORDS)
BUS INTERFACE UNIT
RELOCATION
REGISTER FILE
SEGMENT REGISTERS
AND
INSTRUCTION POINTER
(5 WORDS)
16-BIT ALU
FLAGS
BHE/S7
4 A19/S6
A16/S3
BUS INTERFACE UNIT 16 AD15-AD0
3 INTA, RD, WR
4 DT/R, DEN, ALE, M/IO
6-BYTE
INSTRUCTION
QUEUE
TEST
INTR
NMI
RQ/GT0, 1
HOLD
HLDA
2
CONTROL AND TIMING
2
3
CLK
3
RESET READY MN/MX GND
VCC
LOCK
QS0, QS1
S2, S1, S0
MEMORY INTERFACE
C-BUS
FN2957 Rev 5.00
Jul 13, 2018
BUS
INTERFACE
UNIT
B-BUS
ES
CS
SS
DS
IP
INSTRUCTION
STREAM BYTE
QUEUE
A-BUS
EXECUTION UNIT
CONTROL SYSTEM
EXECUTION
UNIT
AH AL
BH BL
CH CL
DH DL
SP
BP
SI
DI
ARITHMETIC/
LOGIC UNIT
FLAGS
FIGURE 1. FUNCTIONAL DIAGRAM
Page 3 of 39

No Preview Available !

80C86
Pinout
GND
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
NMI
INTR
CLK
GND
40 LD PDIP, CERDIP
TOP VIEW
MAX
1 40 VCC
2 39 AD15
3 38 A16/S3
4 37 A17/S4
5 36 A18/S5
6 35 A19/S6
7 34 BHE/S7
8 33 MN/MX
9 32 RD
10 31 RQ/GT0
11 30 RQ/GT1
12 29 LOCK
13 28 S2
14 27 S1
15 26 S0
16 25 QS0
17 24 QS1
18 23 TEST
19 22 READY
20 21 RESET
(MIN)
(HOLD)
(HLDA)
(WR)
(M/IO)
(DT/R)
(DEN)
(ALE)
(INTA)
Pin Descriptions
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
AD15-AD0 2-16, 39
A19/S6
A18/S5
A17/S4
A16/S3
35-38
I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (t1) and data
(t2, t3, tW, t4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW
during Ti when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.
8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions
(see BHE). These lines are active HIGH and are held at high impedance to the last valid logic level
during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.
O ADDRESS/STATUS: During t1, these are the four most significant address lines for memory
operations. During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during t2, t3, tW, t4. S6 is always LOW. The status of the
interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded
as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge”
or “grant sequence”.
S4 S3 CHARACTERISTICS
0 0 Alternate Data
0 1 Stack
1 0 Code or None
1 1 Data
FN2957 Rev 5.00
Jul 13, 2018
Page 4 of 39

No Preview Available !

80C86
Pin Descriptions (Continued)
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
BHE/S7
34
O BUS HIGH ENABLE/STATUS: During t1 the bus high enable signal (BHE) should be used to enable
data onto the most significant half of the data bus, pins D15-D8. 8-bit oriented devices tied to the upper
half of the bus would normally use BHE to condition chip select functions. BHE is LOW during t1 for
read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of
the bus. The S7 status information is available during t2, t3, and t4. The signal is active LOW, and is
held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold
acknowledge” or “grant sequence”, it is LOW during t1 for the first interrupt acknowledge cycle.
BHE
0
0
1
1
A0 CHARACTERISTICS
0 Whole Word
1 Upper Byte From/to Odd Address
0 Lower Byte From/to Even address
1 None
RD 32
READY
22
INTR
18
TEST
NMI
23
17
RESET
21
CLK
VCC
GND
MN/MX
19
40
1, 20
33
O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending
on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the 80C86 local
bus. RD is active LOW during t2, t3, and tW of any read cycle, and is guaranteed to remain HIGH in
t2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand sequence”.
I READY: The acknowledgment from the addressed memory or I/O device that completes the data
transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Generator to form
READY. This signal is active HIGH. The 80C86 READY input is not synchronized. Correct operation
is not guaranteed if the Setup and Hold Times are not met.
I INTERRUPT REQUEST: A level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to using an interrupt vector lookup table located in system memory. It can be
internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
I TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
I NON-MASKABLE INTERRUPT: An edge triggered input which causes a Type 2 interrupt. A
subroutine is vectored to using an interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the
current instruction. This input is internally synchronized.
I RESET: Causes the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described
in the “Instruction Set Summary” on page 31 when RESET returns LOW. RESET is internally
synchronized.
I CLOCK: Provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for
decoupling.
GND: Ground. Note: Both must be connected. A 0.1µF capacitor between pins 1 and 20 is
recommended for decoupling.
I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
FN2957 Rev 5.00
Jul 13, 2018
Page 5 of 39