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Features
STL100NHS3LL
N-channel 30V - 0.0032- 22A - PowerFLAT™ (6x5)
STripFET™ Power MOSFET plus monolithic Schottky
Preliminary Data
Type
STL100NHS3LL
VDSS
30V
RDS(on)
< 0.0042
ID
22A(1)
1. This value is rated according to Rthj-pcb
Optimal RDS(on) x Qg trade-off @ 4.5V
Reduced switching losses
Reduced conduction losses
t(s)Improved junction-case thermal resistance
ucApplication
rodSwitching applications
te PDescription
leThis product utilizes the latest advanced design
orules of ST’s proprietary STripFET™ technology
sand a proprietary process for integrating a
bmonolithic Schottky diode. The new Power
OMOSFET is optimized for the most important
) -demanding synchronous switch function in DC-
t(sDC converter for Computer and Telecom.
PowerFLAT™(6x5)
Figure 1. Internal schematic diagram
lete ProducTable 1. Device summary
soOrder code
Marking
Ob STL100NHS3LL
L100NHS3LL
Package
PowerFLAT™ (6 x 5)
Packaging
Tape & reel
September 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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Electrical ratings
1 Electrical ratings
STL100NHS3LL
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS Drain-source voltage (VGS = 0)
30 V
VGS Gate-source voltage
± 16 V
ID (1)
Drain current (continuous) at TC = 25°C
22 A
ID (1)
Drain current (continuous) at TC = 100°C
13.7 A
ID(2) Drain current (continuous) at TC = 25°C
100 A
IDM (3) Drain current (pulsed)
88 A
PTOT(1) Total dissipation at TC = 25°C
80 W
PTOT(2) Total dissipation at TC = 25°C
)Tj Operating junction temperature
t(sTstg Storage temperature
c1. The value is rated accordingly to Rthj-pcb
du2. This value is according Rthj-c
ro3. Pulse width limited by safe operating area
te PTable 3. Thermal resistance
leSymbol
Parameter
soRthj-case Thermal resistance junction-case (drain) Max
bRthj-pcb (1) Thermal resistance junction-pcb Max
- O1. When mounted on FR-4 board of 1inch2, 2 oz. Cu., t<10sec
t(s)Table 4. Thermal resistance
ucSymbol
Parameter
rodIAV
Avalanche current, not repetitive (pulse width limited by
Tjmax)
Obsolete PEAS
Single pulse avalanche energy (starting Tj = 25°C,
ID=IAV, VDD=24V)
4
-55 to 150
Value
1.56
31.3
Value
10
1.8
W
°C
Unit
°C/W
°C/W
Unit
A
J
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STL100NHS3LL
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V(BR)DSS
Drain-source breakdown
voltage
ID = 1mA, VGS= 0
30
V
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = 24V
500 µA
IGSS
Gate body leakage current
(VDS = 0)
VDS = ± 16V
±100 nA
VGS(th) Gate threshold voltage
VDS= VGS, ID = 1mA
1
2.5 V
t(s)RDS(on)
Static drain-source on
resistance
roducTable 6. Dynamic
PSymbol
Parameter
leteCiss
oCoss
bsCrss
- OQg
)Qgs
Obsolete Product(sQgd
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
VGS= 10V, ID= 11A
VGS= 4.5V, ID= 11A
VGS=10V, ID=11A@125°C
VGS=4.5V, ID=11A@125°C
0.0032 0.0042
0.004 0.0057
0.005
0.006
Test conditions
Min. Typ. Max. Unit
VDS=25V, f = 1MHz, VGS=0
VDD = 15V, ID = 22A,
VGS = 4.5V
(see Figure 3)
4200
700
46.2
27
8.5
7.2
35
pF
pF
pF
nC
nC
nC
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Electrical characteristics
STL100NHS3LL
Table 7. Switching times
Symbol
Parameter
td(on)
tr
Turn-on delay time
Rise time
td(off)
tf
Turn-off delay time
Fall time
Test conditions
VDD = 15V, ID = 11A
RG= 4.7, VGS= 10V,
(see Figure 2),
(see Figure 7)
VDD = 15V, ID = 11A
RG= 4.7, VGS= 10V,
(see Figure 2)
(see Figure 7)
Min. Typ. Max. Unit
16 ns
45 ns
68 ns
8 ns
Table 8. Source drain diode
Symbol
Parameter
Test conditions
Min. Typ. Max Unit
ISD
t(s)ISDM
VSD (1)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 5A, VGS = 0
uctrr
dQrr
roIRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 22V, di/dt = 100A/µs
VDD = 20V, Tj = 25°C
(see Figure 4)
Obsolete Product(s) - Obsolete P1. Pulsed: Pulse duration = 300µs, duty cycle 1.5%
22 A
88 A
0.75 V
30 ns
30 nC
2A
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STL100NHS3LL
3 Test circuit
Test circuit
Figure 2. Switching times test circuit for
resistive load
Figure 3. Gate charge test circuit
t(s)Figure 4. Test circuit for inductive load
Figure 5. Unclamped inductive load test
cswitching and diode recovery times
circuit
Obsolete Product(s) - Obsolete ProduFigure 6. Unclamped inductive waveform
Figure 7. Switching time waveform
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