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infel..
8080A/8080A-1/8080A-2
8-BIT N-CHANNEL MICROPROCESSOR
TTL Drive Capability
2,..,s (-1:1.3,..,s, -2:1.5 ,..,s) Instruction
Cycle
Powerful Problem Solving Instruction
Set
6 General Purpose Registers and an
Accumulator
16-Blt Program Counter for Directly
Addressing up to 64K Bytes of Memory
16-Blt Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment
Decimal, Binary, and Double Precision
Arithmetic
Ability to Provide Priority Vectored
Interrupts
512 Directly Addressed 110 Ports
Available In EXPRESS
- Standard Temperature Range
Available In 4Q-Lead Cerdlp and Plastic
Packages
(See Packaging Spec. Order #231369)
The Intel 8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip
using Intel's n-channel silicon gate MOS process. This offers the user a high performance solution to control
and processing applications.
The 8080A contains 6 8-bit general purpose working registers and an accumulator. The 6 general purpose
registers may be addressed individually or in pairs providing both single and double precision operators.
Arithmetic and logical instructions set or reset 4 testable flags. A fifth flag provides decimal arithmetic opera-
tion.
The 8080A has an external stack feature wherein any portion of memory may be used as a last in/first out
stack to store/retrieve the contents of the accumulator, flags, program counter, and all of the 6 general
purpose registers. The 16-bit stack pointer controls the addressing of this external stack. This stack gives the
8080A the ability to easily handle multiple level priority interrupts by rapidly storing and restoring processor
status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-lIne address and 8-line
bidirectional data busses are used to facilitate easy interface to memory and I/O. Signals to control the
interface to memory and I/O are provided directly by the 8080A. Ultimate control of the address and data
busses resides with the HOLD signal. It provides the ability to suspend processor operation and force the
address and data busses into a high impedance state. This permits OR-tying these busses with other control-
ling devices for (OMA) direct memory access or multi-processor operation.
NOTE:
The 8080A is functionally and electrically compatible with the Intel 8080.
November 1988
1-1 Order Number. 231453-001
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intel~
8080A/8080A-1/8080A-2
118'"
INTERNAL DATA BUS
t--""::'''--:::+--~''-'':'Il::4
..fGIIT."
..RUY
TIMING
....0
CONTROL
ACII
Figure 1. Block Diagram
AO"D'.-lO..'._""
A,.
GNO
O.
D.
O.
°7
0.
0,
0,0
D.
-SV
RESET
HOLO
'NT
"INTE 0
OBIN
WR
SYNC
+SV
A"
A,.
Au
Au
At.
"-
"-
At
"-
As
Ao
'"+IN
A,
A,
Ao
.,WAIT
RfADY
HLDA
Figure 2. Pin Configuration
231453-2
231453-1
1-2
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intel"
8080A/8080A-1/8080A-2
Symbol
A15-AO
07-0 0
SYNC
OBIN
READY
WAIT
WR
HOLD
HLDA
INTE
INT
RESET1
Vss
Voo
Vee
Vss
(Pt, <1>2
Type
0
I/O
0
0
I
0
0
I
0
0
I
I
Table 1. Pin Description
Name and Function
ADDRESS BUS: The address bus provides the address to memory (up to 64K B-bit
words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.
DATA BUS: The data bus provides bi-directional communication between the CPU,
memory, and I/O devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 80BOA outputs a status word on the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.
DATA BUS IN: The OBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be used to enable the gating of data onto the B080A data
bus from memory or I/O.
READY: The READY signal indicates to the B080A that valid memory or input data is
available on the BOBOA data bus. This signal is used to synchronize the CPU with slower
memory or I/O devices. If after sending an address out the BOBOA does not receive a
READY input, the 80BOA will enter a WAIT state for as long as the READY line is low.
READY can also be used to single step the CPU.
WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.
WRITE: The WR signal is used for memory WRITE or I/O output control. The data on
the data bus is stable while the WR signal is active low (WR = 0).
HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state
allows an external device to gain control of the BOBOA address and data bus as soon as
the 80BOA has completed its use of these busses for the current machine cycle. It is
recognized under the folloWing conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (D7-00)
will be in their high impedance state. The CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.
HOLD ACKNOWLEDGE: The HlDA signal appears in response to the HOLD signal and
indicates that the data and address bus will go to the high impedance state. The HLDA
signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLOA signal appears after the rising edge of <1>2'
INTERRUPT ENABLE: Indicates the content of the internal interrupt enable flip/flop.
This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET signal.
INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable flip/flop is reset it will not honor the request.
RESET: While the RESET signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The INTE and
HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared.
GROUND: Reference.
POWER: +12 ±5% V.
POWER: +5 ±5% V.
POWER: - 5 ± 5% V.
CLOCK PHASES: 2 externally supplied clock phases. (non TTL compatible)
NOTE:
1. The RESET signal must be active for a minimum of 3 clock cycles.
1-3
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intel..
8080A/8080A·1/8080A·2
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias
Storage Temperature
All Input or Output Voltages
with Respect to Vee
Vee, VOO and Vss
with Respect to Ves
Power Dissipation
COC to + 70·C
- 6S·C to + 1S0·C
- 0.3V to + 20V
- 0.3V to + 20V
1.SW
NOTICE: This is a produc&ion data sheet. The specifi-
cations are subject to change without notice.
• WARNING: Strsssing th8 devics beyond the "Absolute
Maximum Rstings" msy CBuse pem7B119nt dsmsg6.
These IUf1 strsss rstings only. Operstion beyond the
"Opersting Conditions" is not f'BCOmmsnded snd ex-
tended exposure beyond th6 "Opersting Conditions"
msy sffeet devics relisbility.
D.C. CHARACTERISTICS
TA = O·C to 70·C, Voo = + 12V ± S%, Vee = + SV ± S%, Vse = - sv ± S%, Vss = OV; unless otherwise
noted
Symbol
Parameter
Min Typ Max Unit
Teat Condition
VILC Clock Input Low Voltage
Vss - 1
Vss + 0.8 V
VIHC Clock Input High Voltage
9.0 Voo + 1 V
VIL Input Low Voltage
Vss - 1
Vss + 0.8 V
VIH Input High Voltage
3.3 Vee + 1 V
VOL Output Low Voltage
O.4S
V } IOL = 1.9 rnA on All Outputs.
VOH Output High Voltage
3.7
V IOH = -15O,..,A.
tOO(AV) Avg. Power Supply Current (VOO)
ICC(AV) Avg. Power Supply Current (Vce>
Iss (AV) Avg. Power Supply Current (Vss)
l~~40 70 rnA
60 80 rnA
TCY = 0.48,...s
0.01 1 rnA
IlL Input Leakage
±10 ,...A Vss :s: VIN :s: Vee
ICL Clock Leakage
±10 ,...A Vss :s: VCLOCK :s: Voo
IOL Data Bus Leakage in Input Mode
-100 ,...A Vss :s: VIN :s: Vss + 0.8V
-2.0 mA Vss + 0.8V :s: VIN :s: Vee
IFL Address and Data Bus Leakage
During HOLD
+10
-100
,...A
VADDR/OATA = Vee
VAODR/OATA = Vss + O.4SV
CAPACITANCE
TA = 2S0C, Vcc = Voo = Vss = OV, Vse = -SV
Symbol Parameter Typ Max Unit Test Condition
CeI> Clock
17 2S pF fe = 1 MHz
Capacitance
CIN Input
6 10 pF Unmeasured Pins
Capacitance
COUT
Output
10 20 pF Returned to Vss
Capacitance
!
L. f------="".,-+-=---+-----i
i
AMIIIENT TEMPERATURE ret
231453-3
Typical Supply Current vs
Temperature, Normalized
=~I SUpply/~TA -O.45%rC
1-4
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intet.
8080A/8080A-1/8080A-2
A.C. CHARACTERISTICS (8080A) TA = O°C to 70°C, VOO = + 12V ± 5%, Vee = + 5V ± 5%,
Vee = - 5V ± 5%, Vss = OV; unless otherwise noted
Symbol
Parameter
Min
Max
-1
Min
-1
Max
-2
Min
-2
Max
Unit
Test
Condition
tey(3) Clock Period
0.48 2.0 0.32 2.0 0.38 2.0 ,...s
1,. tl Clock Rise and Fall Time
0 50 0 25 0 50 ns
t<l>1 <1>1 Pulse Width
60 50 60 ns
t<l>2 <1>2 Pulse Width
t01 Delay </>1 to 4>2
t02 Delay </>1 to </>2
t03 Delay </>1 to 4>2 Leading Edges
tOA Address Output Delay From 4>2
too Data Output Delay From 4>2
220 145
00
70 60
80 60
200
200
175
0
70
70 ns
150 175
180 200
ns
ns
ns
ns
ns
CL = 100 pF
toe Signal Output Delay From 4>1 or 4>2
(SYNC, WR, WAIT, HLDA)
120 110 120 ns CL = 50pF
tOF DBIN Delay From </>2
25 140 25 130 25 140 ns
tOI(1) Delay for Input Bus to Enter Input Mode
tOF tOF tOF ns
tOS1 Data Setup Time During 4>1 and DBIN 30 10 20 ns
tOS2 Data Setup Time to </>2 During DBIN
tOH(1) Data Hold Time From 4>2 and DBIN
150 120 130 ns
(1 ) (1 ) (1 ) ns
tiE INTE Output Delay From 4>2
200 200 200 ns CL = 50pF
tRS READY Setup Time During 4>2
120 90 90 ns
tHS HOLD Setup Time During 4>2
140 120 120 ns
tiS INT Setup Time During 4>2
120 100 100
ns
tH
Hold Time From 4>2 (READY, INT, HOLD)
0
0
0 ns
tFO Delay to Float During Hold
(Address and Data Bus)
120 120 120 ns
tAW Address Stable Prior to WR
(5) (5) (5) ns
tow Output Data Stable Prior to WR
two Output Data Stable From WR
(6) (6) (6) ns
(7) (7) (7) ns
tWA Address Stable From WR
(7) (7) (7) ns
tHF HLDA to Float Delay
(8) (8) (8) ns
tWF WR to Float Delay
(9) (9) (9) ns
tAH Address Hold Time After DBIN During HLDA -20
-20
-20
ns
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
l
C,"100 PF
CL ~ 100 pF
CL Includes Jig Capacitance
231453-4
1-5
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