Table 1. Pin Description
Name and Function
ADDRESS BUS: The address bus provides the address to memory (up to 64K B-bit
words) or denotes the I/O device number for up to 256 input and 256 output devices. Ao
is the least significant address bit.
DATA BUS: The data bus provides bi-directional communication between the CPU,
memory, and I/O devices for instructions and data transfers. Also, during the first clock
cycle of each machine cycle, the 80BOA outputs a status word on the data bus that
describes the current machine cycle. Do is the least significant bit.
SYNCHRONIZING SIGNAL: The SYNC pin provides a signal to indicate the beginning
of each machine cycle.
DATA BUS IN: The OBIN signal indicates to external circuits that the data bus is in the
input mode. This signal should be used to enable the gating of data onto the B080A data
bus from memory or I/O.
READY: The READY signal indicates to the B080A that valid memory or input data is
available on the BOBOA data bus. This signal is used to synchronize the CPU with slower
memory or I/O devices. If after sending an address out the BOBOA does not receive a
READY input, the 80BOA will enter a WAIT state for as long as the READY line is low.
READY can also be used to single step the CPU.
WAIT: The WAIT signal acknowledges that the CPU is in a WAIT state.
WRITE: The WR signal is used for memory WRITE or I/O output control. The data on
the data bus is stable while the WR signal is active low (WR = 0).
HOLD: The HOLD signal requests the CPU to enter the HOLD state. The HOLD state
allows an external device to gain control of the BOBOA address and data bus as soon as
the 80BOA has completed its use of these busses for the current machine cycle. It is
recognized under the folloWing conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active. As a result of
entering the HOLD state the CPU ADDRESS BUS (A15-AO) and DATA BUS (D7-00)
will be in their high impedance state. The CPU acknowledges its state with the HOLD
ACKNOWLEDGE (HLDA) pin.
HOLD ACKNOWLEDGE: The HlDA signal appears in response to the HOLD signal and
indicates that the data and address bus will go to the high impedance state. The HLDA
signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WRITE memory or OUTPUT operation.
In either case, the HLOA signal appears after the rising edge of <1>2'
INTERRUPT ENABLE: Indicates the content of the internal interrupt enable flip/flop.
This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and
inhibits interrupts from being accepted by the CPU when it is reset. It is automatically
reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M1) when an
interrupt is accepted and is also reset by the RESET signal.
INTERRUPT REQUEST: The CPU recognizes an interrupt request on this line at the end
of the current instruction or while halted. If the CPU is in the HOLD state or if the
Interrupt Enable flip/flop is reset it will not honor the request.
RESET: While the RESET signal is activated, the content of the program counter is
cleared. After RESET, the program will start at location 0 in memory. The INTE and
HLDA flip/flops are also reset. Note that the flags, accumulator, stack pointer, and
registers are not cleared.
POWER: +12 ±5% V.
POWER: +5 ±5% V.
POWER: - 5 ± 5% V.
CLOCK PHASES: 2 externally supplied clock phases. (non TTL compatible)
1. The RESET signal must be active for a minimum of 3 clock cycles.
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