Application in ADC Frontend:
Modern Analog-to-Digital Converter (ADC) system often uses differential architecture to suppress the even-order
harmonics, minimize noise interference and keep dynamic range high. The performance of ADC system is heavily
influenced by amplitude and phase imbalances arising from the ADC frontend, especially in high frequency
applications. Anaren’s multi-layer balun B0205F50200AHF offers superb amplitude and phase balance performance
over wide frequency range, translating to excellent SFDR performance of the ADC system. B0205F50200AHF is a
ferrite free design eliminating related inter-modulation and other non-linear effects. B0205F50200AHF has impendence
transforming ratio of 1:4 with voltage gain of 6dB higher than 1:1 balun, which reduces the input drive requirement.
Anaren’s highly repeatable manufacturing process results in little part to part variation, ensuring consistent
performance in production.
A typical ADC front end application is shown below. In conjunction with many high speed ADC ICs, bandwidth of
100MHz to 250MHz can be obtained for -1dB ripple of gain flatness. R1 and R2, in shunt with the input impedance of
ADC, supply the balun with required differential load. The series resistors, R5 and R6 are used to limit the amount of
charge injection from the unbuffered ADC back into the analog input. Optional RC circuits, R3, R4, C4 and C5 further
improve SDFR in many circumstances by supplying an additional current path to neutralize the charge injection. These
values are also chosen to limit or extend the ADC application bandwidth.
ADC frontend schematic for IF 100 MHz to 250MHz
A low frequency solution can be realized by adding additional tuning components C6, L1 and L2. The -1dB ripple of
gain flatness is achieved for IF band of 50MHz to 110MHz.
ADC frontend schematic for IF 50MHz to 110MHz
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