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80C196KB
User’s Guide
November 1990
Order Number 270651-003

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80C196KB USER’S GUIDE
CONTENTS
PAGE CONTENTS
PAGE
1 0 CPU OPERATION
1 1 Memory Controller
1 2 CPU Control
1 3 Internal Timing
2 0 MEMORY SPACE
2 1 Register File
2 2 Special Function Registers
2 3 Reserved Memory Spaces
2 4 Internal ROM and EPROM
2 5 System Bus
3 0 SOFTWARE OVERVIEW
3 1 Operand Types
3 2 Operand Addressing
3 3 Program Status Word
3 4 Instruction Set
3 5 80C196KB Instruction Set
Additions and Differences
3 6 Software Standards and
Conventions
3 7 Software Protection Hints
4 0 PERIPHERAL OVERVIEW
4 1 Pulse Width Modulation Output
(D A)
4 2 Timers
4 3 High Speed Inputs (HSI)
4 4 High Speed Outputs (HSO)
4 5 Serial Port
4 6 A D Converter
4 7 I O Ports
4 8 Watchdog Timer
5 0 INTERRUPTS
5 1 Interrupt Control
5 2 Interrupt Priorities
5 3 Critical Regions
5 4 Interrupt Timing
5 5 Interrupt Summary
1 6 0 Pulse Width Modulation Output
2 (D A)
2 6 1 Analog Outputs
2 7 0 TIMERS
4 7 1 Timer1
4 7 2 Timer2
4
7 3 Sampling on External Timer
Pins
8 7 4 Timer Interrupts
8
9 8 0 HIGH SPEED INPUTS
8 1 HSI Modes
9 8 2 HSI Status
9 8 3 HSI Interrupts
10 8 4 HSI Input Sampling
12 8 5 Initializing the HSI
14
9 0 HIGH SPEED OUTPUTS
22 9 1 HSO Interrupts and Software
Timers
22 9 2 HSO CAM
23 9 3 HSO Status
23
9 4 Clearing the HSO and Locked
Entries
24 9 5 HSO Precautions
24 9 6 PWM Using the HSO
24 9 7 HSO Output Timing
24 10 0 SERIAL PORT
24 10 1 Serial Port Status and Control
26 10 2 Serial Port Interrupts
26 10 3 Serial Port Modes
26 10 4 Multiprocessor
Communications
27
29 11 0 A D CONVERTER
29 11 1 A D Conversion Process
31 11 2 A D Interface Suggestions
31 11 3 The A D Transfer Function
32 11 4 A D Glossary of Terms
33
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80C196KB USER’S GUIDE
CONTENTS
PAGE CONTENTS
PAGE
12 0 I O PORTS
12 1 Input Ports
12 2 Quasi-Bidirectional Ports
12 3 Output Ports
12 4 Ports 3 and 4 AD0 – 15
13 0 MINIMUM HARDWARE
CONSIDERATIONS
13 1 Power Supply
13 2 Noise Protection Tips
13 3 Oscillator and Internal Timings
13 4 Reset and Reset Status
13 5 Minimum Hardware
Connections
14 0 SPECIAL MODES OF
OPERATION
14 1 Idle Mode
14 2 Powerdown Mode
14 3 ONCE and Test Modes
60 15 0 EXTERNAL MEMORY
60 INTERFACING
60 15 1 Bus Operation
62 15 2 Chip Configuration Register
63 15 3 Bus Width
15 4 HOLD HLDA Protocol
71
71
72
75
76
64 15 5 AC Timing Explanations
64 15 6 Memory System Examples
64 15 7 I O Port Reconstruction
78
83
85
64 16 0 USING THE EPROM
85
65 16 1 Power-Up and Power-Down
85
16 2 Reserved Locations
68 16 3 Programming Pulse Width
Register (PPW)
86
87
69 16 4 Auto Configuration Byte
69 Programming Mode
69 16 5 Auto Programming Mode
70 16 6 Slave Programming Mode
16 7 Run-Time Programming
88
88
90
92
16 8 ROM EPROM Memory Protection
Options
93
16 9 Algorithms
94

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80C196KB USER’S GUIDE
The 80C196KB family is a CHMOS branch of the
MCS -96 family Other members of the MCS-96 fami-
ly include the 8096BH and 8098 All of the MCS-96
components share a common instruction set and archi-
tecture However the CHMOS components have en-
hancements to provide higher performance at lower
power consumptions To further decrease power usage
these parts can be placed into idle and powerdown
modes
MCS-96 family members are all high-performance mi-
crocontrollers with a 16-bit CPU and at least 230 bytes
of on-chip RAM They are register-to-register ma-
chines so no accumulator is needed and most opera-
tions can be quickly performed from or to any of the
registers In addition the register operations can con-
trol the many peripherals which are available on the
chips These peripherals include a serial port A D con-
verter PWM output up to 48 I O lines and a High-
Speed I O subsystem which has 2 16-bit timer coun-
ters an 8-level input capture FIFO and an 8-entry pro-
grammable output generator
Typical applications for MCS-96 products are closed-
loop control and mid-range digital signal processing
MCS-96 products are being used in modems motor
controls printers engine controls photocopiers anti-
lock brakes air conditioner temperature controls disk
drives and medical instrumentation
There are many members of the 80C196KB family so
to provide easier reading this manual will refer to the
80C196KB family generically as the 80C196KB
Where information applies only to specific components
it will be clearly indicated
The 80C196KB can be separated into four sections for
the purpose of describing its operation A block dia-
gram is shown in Figure 1-1 There is the CPU and
architecture the instruction set the peripherals and the
bus unit Each of the sections will be sub-divided as the
discussion progresses Let us first examine the CPU
1 0 CPU OPERATION
The major components of the CPU on the 80C196KB
are the Register File and the Register Arithmetic Log-
ic Unit (RALU) Communication with the outside
world is done through either the Special Function Reg-
isters (SFRs) or the Memory Controller The RALU
does not use an accumulator Instead it operates di-
rectly on the 256-byte register space made up of the
Register File and the SFRs Efficient I O operations
are possible by directly controlling the I O through the
SFRs The main benefits of this structure are the ability
to quickly change context absence of accumulator bot-
tleneck and fast throughput and I O times
Figure 1-1 80C196KB Block Diagram
270651 – 1
1