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PF535-07
E0C6282
4-bit Single Chip Microcomputer
WOiPdpereorVdauoticlottansge
q Core CPU Architecture
q SVD Circuit/Comparator
q Melody Circuit
q 288 Segments for LCD
s DESCRIPTION
The E0C6282 is an advanced single-chip CMOS 4-bit microcomputer consisting of the E0C6200A CMOS 4-bit
core CPU. It also contains the ROM, RAM, LCD driver circuit, time base counter, stopwatch counter and melody
generation circuit.
The E0C6282 provides an excellent solution for low-power consumption systems with clock functions.
s FEATURES
q CMOS LSI ............................................. 4-bit parallel processing
q Clock ..................................................... 32.768kHz/1MHz
q Instruction set ........................................ 100 instructions
q Instruction cycle time ............................ 153µsec, 214µsec or 366µsec at 32kHz (depending on instruction)
5µsec, 7µsec or 12µsec at 1MHz (depending on instruction)
q ROM capacity ....................................... 2,048 × 12 bits
q RAM capacity ........................................ 224 × 4 bits (include segment memory)
q Input port ............................................... 5 bits (pull-down resistors are available by mask option)
q Output port ............................................ 5 bits (general purpose port)
2 bits (for melody output): MO, MO (also used as the external CR
connecting terminal for envelope)
1 bit (for clock output: frequency can be selected from 256Hz
through 32kHz by mask option)
q Built-in stopwatch timer
q Built-in analog comparator
q I/O port .................................................. 4 bits
q LCD driver ............................................. 42 segments × 4 commons/38 segments × 8 commons
(1/4 or 1/8 duty is selectable by mask option)
q Built-in supply voltage detection (SVD) circuit
q Built-in melody generation circuit .......... Melody memory capacity : 128 words
Interval memory capacity : 32 words (including one pause note)
q Interrupts ............................................... External : Input interrupt
2 lines
Internal : Timer interrupt
2 lines
Melody completion interrupt 1 line
q Current consumption ............................ E0C6282/62L82
HALT mode (32.768kHz)
: 1.5µA (Typ.)
OPERATING mode (32.768kHz) : 4.0µA (Typ.)
E0C62A82
OPERATING mode (1MHz)
: 150µA (Typ.)
q Package ................................................ QFP5-80pin (plastic), QFP14-80pin (plastic)
Die form
s LINE UP
Model
E0C62L82
E0C6282
E0C62A82
Supply voltage
1.5V (1.1V to 3.5V)
3.0V (2.2V to 5.5V)
3.0V (2.2V to 5.5V)
Clock
32kHz (Crystal or CR oscillation)
32kHz (Crystal or CR oscillation)
32kHz (Crystal or CR oscillation) & 1MHz (Ceramic or CR oscillation)
SEIKO EPSON CORPORATION
1

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E0C6282
s BLOCK DIAGRAM
ROM
2,048 words x 12 bits
OSC
System Reset
Control
SEG0
COM7 / SEG38
COM6 / SEG39
COM5 / SEG40
COM4 / SEG41
COM0
VDD
VL1~4
CA~CD
VS1
VSS
CMPP
CMPM
Core CPU E0C6200A
RAM
224 words x 4 bits
LCD Driver
Power
Controller
Comparator
& SVD
Interrupt
Generator
Input Port
Test Port
I/O Port
Output Port
Timer
Stop Watch
Melody
K00~03, K10
TEST
P00~03
R00~03, R10, R11
MO
R12
s PIN CONFIGURATION
QFP5-80pin
64
65
41
40
E0C6282
INDEX
80
1
25
24
QFP14-80pin
60
61
41
40
E0C6282
INDEX
80
1
21
20
2
No. Pin name
1 VDD
2 TEST
3 SEG0
4 SEG1
5 SEG2
6 SEG3
7 SEG4
8 SEG5
9 SEG6
10 SEG7
11 SEG8
12 SEG9
13 SEG10
14 SEG11
15 SEG12
16 SEG13
No. Pin name
17 SEG14
18 SEG15
19 SEG16
20 SEG17
21 SEG18
22 SEG19
23 R03
24 R02
25 R01
26 R00
27 MO
28 R12
29 R11
30 R10
31 K10
32 K03
No. Pin name
33 K02
34 K01
35 K00
36 RESET
37 CMPP
38 CMPM
39 COM3
40 COM2
41 COM1
42 COM0
43 SEG22
44 SEG23
45 SEG24
46 SEG25
47 SEG26
48 SEG27
No. Pin name No. Pin name
49 SEG28
65 P01
50 SEG29
66 P00
51 SEG30
67 CD
52 SEG31
68 CC
53 SEG32
69 CB
54 SEG33
70 CA
55 SEG34
71 VL4
56 SEG35
72 VL3
57 SEG36
73 VL2
58 SEG37
74 VL1
59 SEG38/COM7 75 VSS
60 SEG39/COM6 76 OSC4
61 SEG40/COM5 77 OSC3
62 SEG41/COM4 78 VS1
63 P03
79 OSC2
64 P02
80 OSC1
No. Pin name
1 SEG0
2 SEG1
3 SEG2
4 SEG3
5 SEG4
6 SEG5
7 SEG6
8 SEG7
9 SEG8
10 SEG9
11 SEG10
12 SEG11
13 SEG12
14 SEG13
15 SEG14
16 SEG15
No. Pin name
17 SEG16
18 SEG17
19 SEG18
20 SEG19
21 R03
22 R02
23 R01
24 R00
25 MO
26 R12
27 R11
28 R10
29 K10
30 K03
31 K02
32 K01
No. Pin name
33 K00
34 RESET
35 CMPP
36 CMPM
37 COM3
38 COM2
39 COM1
40 COM0
41 SEG22
42 SEG23
43 SEG24
44 SEG25
45 SEG26
46 SEG27
47 SEG28
48 SEG29
No. Pin name No. Pin name
49 SEG30
65 CD
50 SEG31
66 CC
51 SEG32
67 CB
52 SEG33
68 CA
53 SEG34
69 VL4
54 SEG35
70 VL3
55 SEG36
71 VL2
56 SEG37
72 VL1
57 SEG38/COM7 73 VSS
58 SEG39/COM6 74 OSC4
59 SEG40/COM5 75 OSC3
60 SEG41/COM4 76 VS1
61 P03
77 OSC2
62 P02
78 OSC1
63 P01
79 VDD
64 P00
80 TEST

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E0C6282
s PIN DESCRIPTION
Pin name
VDD
VSS
VS1
VL1–VL4
CA–CD
OSC1
OSC2
OSC3
OSC4
K00–K00, K10
P00–P03
R00–R03
R10
R11
R12
MO
CMPP
CMPM
SEG0–37
COM0–3
SEG38–41
COM4–7
RESET
TEST
Pin No.
QFP5-80pin QFP14-80pin
In/Out
1 79 I
75 73 I
78 76 –
71–74
69–72
67–70
65–68
80 78 I
79 77 O
77 75 I
76 74 O
32–35, 31 30–33, 29
I
63–66
61–64
I/O
23–26
21–24
O
30 28 O
29 27 O
28 26 O
27 25 O
37 35 I
38 36 I
3–22,
1–20,
O
43–58
41–56
39–42
37–40
O
59–62
57–60
O
36 34 I
2 80 I
Function
Power source (+) terminal
Power source (-) terminal
Oscillation and internal logic system regulated voltage output terminal
LCD system power source terminal
LCD system booster capacitor connecting terminal
Crystal or CR oscillation input terminal
Crystal or CR oscillation output terminal
Ceramic or CR oscillation input terminal (62A82 only)
Ceramic or CR oscillation output terminal (62A82 only)
Input terminal
I/O terminal
Output terminal
Output terminal (FOUT output available by mask option)
Output terminal
Output terminal (Melody inverted output and envelope function available by mask option)
Melody signal output terminal
Analog comparator non-inverted input terminal
Analog comparator inverted input terminal
LCD segment output terminal (Convertible to DC output by mask option)
SEG20 and 21 may be used only when the chip has been supplied
LCD common output terminal
LCD segment output terminal when 1/4 duty is selected
LCD common output terminal when 1/8 duty is selected
Initial reset input terminal
Test input terminal
s ELECTRICAL CHARACTERISTICS
q Absolute Maximum Ratings
(VDD=0V)
Rating
Symbol
Value
Unit
Supply voltage
VSS
-6.0 to 0.5
V
Input voltage (1)
VI
VSS - 0.3 to 0.5
V
Input voltage (2)
VIOSC
VS1 - 0.3 to 0.5
V
Permissible total output current *1 ΣIVSS 10 mA
Operating temperature
Topr
-20 to 70
°C
Storage temperature
Tstg
-65 to 150
°C
Soldering temperature / Time
Tsol
260°C, 10sec (lead section)
Permissible dissipation *2
PD
250 mW
1: The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is draw in).
2: In case of plastic package (QFP5-80pin, QFP14-80pin).
q Recommended Operating Conditions
E0C6282
Condition
Supply voltage
Oscillation frequency
Symbol
VSS VDD=0V
fOSC1
Remark
(Ta=-20 to 70°C)
Min.
Typ.
Max.
Unit
-5.5 -3.0 -2.2 V
– 32.768 –
kHz
E0C62L82
Condition
Symbol
Remark
Min. Typ.
Supply voltage
VSS VDD=0V
-3.5 -1.5
VDD=0V, With software control *1
-3.5 -1.5
VDD=0V, When the analog comparator is used -3.5 -1.5
Oscillation frequency
fOSC1
– 32.768
1: When switching to heavy load protection mode. The SVD circuit and analog voltage comparator are turned OFF.
2: The possibility of LCD panel display differs depending on the characteristics of the LCD panel.
E0C62A82
Condition
Supply voltage
Oscillation frequency (1)
Oscillation frequency (2)
Symbol
VSS VDD=0V
fOSC1
fOSC3 duty 50±5%
Remark
Min. Typ.
-5.5 -3.0
– 32.768
– 1,000
(Ta=-20 to 70°C)
Max.
Unit
-1.1 V
-0.9 *2 V
-1.3 V
– kHz
(Ta=-20 to 70°C)
Max.
Unit
-2.2 V
– kHz
– kHz
3

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E0C6282
q DC Characteristics
E0C6282/62A82
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
High level input voltage (1) VIH1
K00–K03, K10, P00–P03 0.2•VSS
0V
High level input voltage (2) VIH2
RESET, TEST
0.10•VSS
0V
Low level input voltage (1) VIL1
K00–K03, K10, P00–P03 VSS
0.8•VSS
V
Low level input voltage (2) VIL2
RESET, TEST
VSS
0.90•VSS
V
High level input current (1) IIH1 VIH1=0V
K00–K03, K10, P00–P03
0
0.5 µA
No pull down resistor
CMPP, CMPM
High level input current (2) IIH2 VIH2=0V
K00–K03, K10
5
16 µA
With pull down resistor
High level input current (3) IIH3 VIH3=0V
P00–P03
30 100 µA
With pull down resistor
RESET, TEST
Low level input current
IIL VIL=VSS
K00–K03, K10, P00–P03 -0.5
0 µA
CMPP, CMPM
RESET, TEST
High level output current (1) IOH1 VOH1=0.1•VSS
R11
-1.0 mA
High level output current (2) IOH2 VOH2=0.1•VSS
R00–R03, R10, P00–P03
-1.0 mA
High level output current (3) IOH3 VOH3=0.1•VSS
MO, R12
-2.0 mA
Low level output current (1) IOL1 VOL1=0.9•VSS
R11
3.0
mA
Low level output current (2) IOL2 VOL2=0.9•VSS
R00–R03, R10, P00–P03 3.0
mA
Low level output current (3) IOL3 VOL3=0.9•VSS
MO, R12
4.5
mA
Common output current
IOH4 VOH4=-0.05V
COM0–COM3
-3 µA
1/4 duty IOL4 VOL4=VL3+0.05V
3 µA
Segment output current
IOH5 VOH5=-0.05V
SEG0–SEG41
-3 µA
(during LCD output)1/4 duty IOL5 VOL5=VL3+0.05V
3 µA
Segment output current
IOH6 VOH6=0.1•VSS
SEG0–SEG41
-300
µA
(during DC output) 1/4 duty IOL6 VOL6=0.9•VSS
300 µA
Common output current
IOH7 VOH7=-0.05V
COM0–COM7
-3 µA
1/8 duty IOL7 VOL7=VL4+0.05V
3 µA
Segment output current
IOH8 VOH8=-0.05V
SEG0–SEG37
-3 µA
(during LCD output)1/8 duty IOL8 VOL8=VL4+0.05V
3 µA
Segment output current
IOH9 VOH9=0.1•VSS
SEG0–SEG37
-300
µA
(during DC output) 1/8 duty IOL9 VOL9=0.9•VSS
300 µA
E0C62L82
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
High level input voltage (1) VIH1
K00–K03, K10, P00–P03 0.2•VSS
0V
High level input voltage (2) VIH2
RESET, TEST
0.10•VSS
0V
Low level input voltage (1) VIL1
K00–K03, K10, P00–P03 VSS
0.8•VSS
V
Low level input voltage (2) VIL2
RESET, TEST
VSS
0.90•VSS
V
High level input current (1) IIH1 VIH1=0V
K00–K03, K10, P00–P03
0
0.5 µA
No pull down resistor
CMPP, CMPM
High level input current (2) IIH2 VIH2=0V
K00–K03, K10
2.0
10 µA
With pull down resistor
High level input current (3) IIH3 VIH3=0V
P00–P03
9.0 60 µA
With pull down resistor
RESET, TEST
Low level input current
IIL VIL=VSS
K00–K03, K10, P00–P03 -0.5
0 µA
CMPP, CMPM
RESET, TEST
High level output current (1) IOH1 VOH1=0.1•VSS
R11
-450
µA
High level output current (2) IOH2 VOH2=0.1•VSS
R00–R03, R10, P00–P03
-200
µA
High level output current (3) IOH3 VOH3=0.1•VSS
MO, R12
-0.8 mA
High level output current (4) IOH4 VOH4=0.1•VSS
MO
-0.4 mA
When envelope is used
(R12=Normal H level)
Low level output current (1) IOL1 VOL1=0.9•VSS
R11
1,300
µA
Low level output current (2) IOL2 VOL2=0.9•VSS
R00–R03, R10, P00–P03 700
µA
Low level output current (3) IOL3 VOL3=0.9•VSS
MO, R12
1.5
mA
Low level output current (4) IOL4 VOL4=0.9•VSS
MO
750
µA
When envelope is used
(R12=Normal L level)
Common output current
IOH5 VOH5=-0.05V
COM0–COM3
-3 µA
1/4 duty IOL5 VOL5=VL3+0.05V
3 µA
Segment output current
IOH6 VOH6=-0.05V
SEG0–SEG41
-3 µA
(during LCD output)1/4 duty IOL6 VOL6=VL3+0.05V
3 µA
Segment output current
IOH7 VOH7=0.1•VSS
SEG0–SEG41
-100
µA
(during DC output) 1/4 duty IOL7 VOL7=0.9•VSS
130 µA
Common output current
IOH8 VOH8=-0.05V
COM0–COM7
-3 µA
1/8 duty IOL8 VOL8=VL4+0.05V
3 µA
Segment output current
IOH9 VOH9=-0.05V
SEG0–SEG37
-3 µA
(during LCD output)1/8 duty IOL9 VOL9=VL4+0.05V
3 µA
Segment output current
IOH10 VOH10=0.1•VSS
SEG0–SEG37
-100
µA
(during DC output) 1/8 duty IOL10 VOL10=0.9•VSS
130 µA
4

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E0C6282
q Analog Circuit Characteristics and Current Consumption
E0C6282 (Normal Operating Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connect 1Mload resistor between VDD and VL1
(without panel load)
VL2 Connect 1Mload resistor between VDD and VL2
0.5•VL2
-0.1
-2.25
-2.10
0.5•VL2
+0.1
-1.95
V
V
SVD voltage
SVD circuit response time
Analog comparator
input voltage
VL3
VL4
VSVD
tSVD
VIP
VIM
(without panel load)
Connect 1Mload resistor between VDD and VL3
(without panel load)
Connect 1Mload resistor between VDD and VL4
(without panel load)
Noninverted input (CMPP)
Inverted input (CMPM)
3•VL1
-0.1
4•VL1
-0.1
-2.55
VSS+0.3
-2.40
3•VL1
×0.9
4•VL1
×0.9
-2.25
100
VDD-0.9
V
V
V
µS
V
Analog comparator
VOF
10 mV
offset voltage
Analog comparator
tCMP VIP=-1.5V, VIM=VIP±15mV
1 mS
response time
Current consumption
IOP1 During HALT *1
Without panel load
During operation *1
OSC1 is crystal oscillation
IOP2 During HALT *1
Without panel load
During operation *1
OSC1 is CR oscillation
1: The SVD circuit and analog voltage comparator are turned OFF.
1.5 3.0 µA
4.0 7.0 µA
6.0
10.5
µA
8.7
14.0
µA
E0C6282 (Heavy Load Protection Mode)
(Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connect 1Mload resistor between VDD and VL1
(without panel load)
VL2 Connect 1Mload resistor between VDD and VL2
(without panel load)
0.5•VL2
-0.1
-2.25
-2.10
0.5•VL2
+0.1
-1.95
V
V
SVD voltage
SVD circuit response time
Analog comparator
VL3
VL4
VSVD
tSVD
VIP
Connect 1Mload resistor between VDD and VL3
(without panel load)
Connect 1Mload resistor between VDD and VL4
(without panel load)
Noninverted input (CMPP)
3•VL1
-0.1
4•VL1
-0.1
-2.55
VSS+0.3
-2.40
3•VL1
×0.9
4•VL1
×0.9
-2.25
100
VDD-0.9
V
V
V
µS
V
input voltage
Analog comparator
VIM
VOF
Inverted input (CMPM)
10 mV
offset voltage
Analog comparator
response time
tCMP VIP=-1.5V, VIM=VIP±15mV
1 mS
Current consumption
IOP1 During HALT *1
Without panel load
During operation *1
OSC1 is crystal oscillation
IOP2 During HALT *1
Without panel load
During operation *1
OSC1 is CR oscillation
1: The SVD circuit and analog voltage comparator are turned OFF.
11.5
14.0
16.0
18.7
33.0
37.0
40.5
44.0
µA
µA
µA
µA
E0C62L82 (Normal Operating Mode)
(Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25°C, CG=25pF, VS1/VL1–VL4 are internal voltage, C1–C6=0.1µF)
Characteristic
Symbol
Condition
Min.
Typ.
Max.
Unit
Internal voltage
VL1 Connect 1Mload resistor between VDD and VL1
-1.15
-1.05
-0.95
V
(without panel load)
VL2 Connect 1Mload resistor between VDD and VL2
(without panel load)
VL3 Connect 1Mload resistor between VDD and VL3
2•VL1
-0.1
3•VL1
2•VL1
×0.9
3•VL1
V
V
(without panel load)
VL4 Connect 1Mload resistor between VDD and VL4
(without panel load)
-0.1
4•VL1
-0.1
×0.9
4•VL1
×0.9
V
SVD voltage
SVD circuit response time
VSVD
tSVD
-1.30
-1.20
-1.10
100
V
µS
Analog comparator
VIP Noninverted input (CMPP)
VSS+0.3
VDD-0.9
V
input voltage
VIM Inverted input (CMPM)
Analog comparator
VOF
20 mV
offset voltage
Analog comparator
tCMP VIP=-1.1V, VIM=VIP±30mV
1 mS
response time
Current consumption
IOP1 During HALT *1
Without panel load
1.5 3.0 µA
IOP2
During operation *1
During HALT *1
During operation *1
OSC1 is crystal oscillation
Without panel load
OSC1 is CR oscillation
4.0 7.0 µA
6.0
10.5
µA
8.7
14.0
µA
1: The SVD circuit and analog voltage comparator are turned OFF.
5