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ISL6726
Active Clamp Forward PWM Controller
The ISL6726 is a highly featured single-ended PWM controller
intended for applications using the active clamp forward
converter topology in either n- or p-channel active clamp
configurations, the asymmetric half-bridge topology, and the
standard forward topologies with synchronous rectification. It
is a current-mode PWM controller with many features
designed to simplify its use. Among its many features are a
precision oscillator which allows accurate control of the
deadtime and maximum duty cycle, bi-directional
synchronization with 180° phase shift for interleaving
applications, adjustable soft-start and soft-stop, a low power
disable mode, and average current limit for “brick-wall”
overcurrent protection.
This advanced BiCMOS design features low start-up and
operating currents, adjustable switching frequency to greater
than 1MHz, high current FET drivers, and very low propagation
delays for a fast response to overcurrent faults.
Applications
• Telecom and Datacom Power Supplies
• AC/DC Power Supplies
• Battery Chargers
DATASHEET
FN7654
Rev 0.00
January 31, 2011
Features
• Precision Maximum Duty Cycle and Deadtime Control
• 125µA Typical Start-up Current
• Adjustable Peak and Average Current Limit Protection
• Programmable Oscillator Frequency
• Bi-Directional Synchronization with 180° Phase Shift for
Interleaved Converter Applications
• Adjustable Soft-Start and Selectable Soft-Stop
• Selectable Minimum Duty Cycle Clamp for Synchronous
Rectifier Applications
• Programmable Slope Compensation
• Supports N- and P-Channel Active Clamp FETs
• Programmable Switch Timing Between Main and Active
Clamp Outputs
• Programmable Undervoltage Lock-Out (UV)
• Input Voltage Dependent Duty Cycle Clamp
• ENABLE Input with Low Power Disable
• Internal Over-Temperature Protection
• Pb-Free (RoHS Compliant)
+VIN
+VIN
-VIN
LEVEL
SHIFT
OUTAC
OUTM
OUTAC
N- or P- CHANNEL ACTIVE CLAMP FORWARD
-VIN
OUTM
LEVEL
SHIFT
OUTAC
ASYMMETRIC HALF-BRIDGE
FN7654 Rev 0.00
January 31, 2011
Page 1 of 21

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ISL6726
Pin Configuration
ISL6726
(20 LD QSOP)
TOP VIEW
SYNC 1
DCLIM 2
UV 3
ENABLE 4
RTC 5
CT 6
ISET 7
VERR 8
FB 9
CS 10
20 SS
19 MODE
18 DELAY
17 VREF
16 GND
15 OUTM
14 VDD
13 OUTAC
12 SLOPE
11 IOUT
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
SYMBOL
SYNC
DCLIM
UV
ENABLE
RTC
CT
ISET
VERR
FB
CS
IOUT
DESCRIPTION
A bi-directional edge-sensitive signal used to synchronize multiple devices together. If the SYNC pins of two units are connected, they
will synchronize 180 degrees out of phase with each other. This feature facilitates the design of interleaved topologies. If more than
two units are connected, one will be the master unit and the rest will be slave units. All of the slave units will synchronize 180 degrees
out-of-phase with the master. The master designation is not fixed or predetermined and is self-arbitrating. The master is determined
by the fastest running oscillator on a dynamic basis. SYNC may also be used to synchronize to an external clock.
Used in conjunction with UV, DCLIM creates a duty cycle clamp that is dependent on the input voltage. As the input voltage increases,
the maximum allowed duty cycle decreases. This feature is necessary in the active clamp forward to help prevent transformer core
saturation during transients. A resistor divider from VREF sets the threshold of DCLIM.
Sets the user programmable undervoltage threshold. Placing a resistor divider from the input voltage to ground and set to 1.00V
determines the minimum operating voltage. The amount of hysteresis is determined by an internal current source and set by the
external impedance of the divider. The current source is active when UV is below 1V.
A logic level signal used to enable the IC. When the input is open, the IC is enabled and a soft-start cycle begins if no fault conditions
are present. When pulled low, the outputs are disabled and the IC enters a low power sleep state. If soft-stop is enabled, a logic “0”
on ENABLE forces a soft-stop prior to entering the low power sleep state.
The oscillator timing capacitor charge/discharge current control pin. A resistor is connected between this pin and GND and
determines the magnitude of the charge and discharge current. The charge current is nominally 2x the current flowing into the
resistor. The discharge current is nominally 8x the current flowing into the resistor. The ratio of the charge to discharge current is
fixed and sets the maximum duty cycle at 80%.
The oscillator timing capacitor is connected between this pin and GND.
Controls the peak and average current limit thresholds. A voltage up to 1.0V may be applied to ISET.
The error voltage input to the PWM comparator and the compensation connection for the average current loop control. VERR
requires an external pull-up resistor to VREF. A typical application connects the photo-transistor output of an opto-coupler between
VERR and GND.
FB is the inverting input to the average current error amplifier (IEA). The amplifier is used as the error amplifier for the average
current limit control loop. If the amplifier is not used, FB should be grounded. The amplifier is normally configured as an integrator.
The current sense input to the IC. Provides information to the PWM, the peak overcurrent protection comparators, and the average
current limit circuitry. The CS pin is shorted to GND when the PWM output pulse terminates. Depending on the current sensing
source impedance, a series input resistor may be required due to the delay between the internal logic and the turn off of the external
power switch.
Output of the sample and hold buffer amplifier that captures and averages the CS signal. With a nominal 4x multiplier and the ability
to scale the signal externally with a resistor divider, the average current limit can be set independently of the peak current limit.
FN7654 Rev 0.00
January 31, 2011
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ISL6726
Pin Descriptions (Continued)
PIN #
12
13
14
15
16
17
18
19
20
SYMBOL
SLOPE
OUTAC
VDD
OUTM
GND
VREF
DELAY
MODE
SS
DESCRIPTION
A slope compensation capacitor is connected between SLOPE and GND. A current source of 100µA charges the capacitor during
the On time and discharges it during the Off time. The amplitude of the signal is multiplied by a gain of 0.2 and summed with the
CS input.
The Active Clamp output for driving an external power switch. OUTAC is capable of driving either a p- or n- channel clamp device and
is configured by DELAY.
VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the
VDD and GND pins as possible. VDD is monitored for undervoltage (UVLO). When VDD is below the UVLO threshold, the IC is disabled
and the reference voltage, VREF, is turned off.
The main PWM output for driving an external power switch.
Logic and power ground for this device. Due to high peak currents and high frequency operation, a low impedance layout is
necessary. Ground planes and short traces are highly recommended.
The 5.00V reference voltage output having a -2/+1.5% tolerance over line, load and operating temperature. Bypass to GND
with a 0.1µF to 2.2µF low ESR capacitor. VREF can source up to 10mA.
The DELAY pin configures OUTAC for either n-channel or p-channel drive compatibility by setting the phase and the duration when
both the main and active clamp outputs are off. A resistor from DELAY to VREF sets an out-of-phase (non-overlap) relationship for
an n-channel clamp device with adjustable deadtime. A resistor from DELAY to GND sets an in-phase (overlap) relationship for a
p-channel clamp device with an adjustable symmetric non-overlap duration between OUTM and OUTAC.
The MODE pin configures the IC for standard or synchronous rectification operation. If MODE is connected to VREF, standard
rectification operation is selected. Soft-stop and the minimum duty cycle clamp are disabled. If MODE is connected to GND,
synchronous rectification operation is enabled allowing soft-stop and the minimum duty cycle clamp to function.
Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start and soft-stop. The value of the
SS capacitor determines the rate of increase and decrease of the duty cycle during start-up and soft-stop. Soft-stop is
enabled/disabled by MODE.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-free)
PKG. DWG.
#
ISL6726AAZ
ISL6726 AAZ
-40 to +105
20 Ld QSOP
M20.15
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6726. For more information on MSL, please see Technical Brief TB363.
FN7654 Rev 0.00
January 31, 2011
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Internal Architecture
VREF
VDD
UVLOBIAS
GND
UVLO
INTERNAL
OT SHUTDOWN
130 - 150 C
VREF
5.00 V
1%
ON
DISABLE
UV
1.00 V
+
-
INHIBIT
EXT. SYNC
RTC
IRTC
OSCILLATOR
SYNC
SYNC
Bi-Directional
SYNC Circuit
SYNC OUT
Phase-Shifted
180 º
CLK
VREF
ICH
ON
CT
DCLIM
IDCH
ON
____
CLK CT CLK
+
-
ISET
CS
SLOPE
VERR
+ OC DETECT
-
VREF
SLOPE
VERROR
CS OC
PWM
DUTY LIMIT
PWM OUT
SOFT-START
MODE
CLK
PWM
OUTPUT DELAY CONTROL
AND
STEERING LOGIC
OUT
DELAY
OUTCLAMP
VDD
OUTM
DELAY
OUTAC
CS AVERAGE
CURRENT LIMIT
IOUT
IOUT
CURRENT
AMPLIFIER
-
+ ISET
FB
LEADING EDGE BLANKING
DISABLE
VREF
INHIBIT
UVLOBIAS
SOFT-START/
SOFT-STOP
ENABLE
SS
MODE

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Typical Application Using ISL6726 - Active Clamp Forward with Synchronous Rectification
VIN+
VIN-
SYNC
ON/OFF
VCC (+10V)
R1
R2 R3
T1
T2
Q3
L1
Q4 +
C13
CR1
C12
Q1
C1
R22
Q2
R14
CR2
1 SYNC
SS 20
2 DCLIM U1 MODE 19
3 UV
DELAY 18
4 ENABLE VREF 17
5 RTC
GND 16
6 CT
OUTM 15
C5
7 ISET
VDD 14
R8
R5
8 VERR
9 FB
OUTAC 13
SLOPE 12
10 CS
IOUT 11
R4
C2 R7
R13
C9
R22
Q5
R23
R24
C14
R25
T2 CR3
C15
R16
R15
R17
R18 R19
C11
R10
C3 R6 R9
C4 C6 C7
R11 R12
C8
U2
VR1
R21 C10
U4 R20
+Vout
RETURN