(20 LD QSOP)
A bi-directional edge-sensitive signal used to synchronize multiple devices together. If the SYNC pins of two units are connected, they
will synchronize 180 degrees out of phase with each other. This feature facilitates the design of interleaved topologies. If more than
two units are connected, one will be the master unit and the rest will be slave units. All of the slave units will synchronize 180 degrees
out-of-phase with the master. The master designation is not fixed or predetermined and is self-arbitrating. The master is determined
by the fastest running oscillator on a dynamic basis. SYNC may also be used to synchronize to an external clock.
Used in conjunction with UV, DCLIM creates a duty cycle clamp that is dependent on the input voltage. As the input voltage increases,
the maximum allowed duty cycle decreases. This feature is necessary in the active clamp forward to help prevent transformer core
saturation during transients. A resistor divider from VREF sets the threshold of DCLIM.
Sets the user programmable undervoltage threshold. Placing a resistor divider from the input voltage to ground and set to 1.00V
determines the minimum operating voltage. The amount of hysteresis is determined by an internal current source and set by the
external impedance of the divider. The current source is active when UV is below 1V.
A logic level signal used to enable the IC. When the input is open, the IC is enabled and a soft-start cycle begins if no fault conditions
are present. When pulled low, the outputs are disabled and the IC enters a low power sleep state. If soft-stop is enabled, a logic “0”
on ENABLE forces a soft-stop prior to entering the low power sleep state.
The oscillator timing capacitor charge/discharge current control pin. A resistor is connected between this pin and GND and
determines the magnitude of the charge and discharge current. The charge current is nominally 2x the current flowing into the
resistor. The discharge current is nominally 8x the current flowing into the resistor. The ratio of the charge to discharge current is
fixed and sets the maximum duty cycle at 80%.
The oscillator timing capacitor is connected between this pin and GND.
Controls the peak and average current limit thresholds. A voltage up to 1.0V may be applied to ISET.
The error voltage input to the PWM comparator and the compensation connection for the average current loop control. VERR
requires an external pull-up resistor to VREF. A typical application connects the photo-transistor output of an opto-coupler between
VERR and GND.
FB is the inverting input to the average current error amplifier (IEA). The amplifier is used as the error amplifier for the average
current limit control loop. If the amplifier is not used, FB should be grounded. The amplifier is normally configured as an integrator.
The current sense input to the IC. Provides information to the PWM, the peak overcurrent protection comparators, and the average
current limit circuitry. The CS pin is shorted to GND when the PWM output pulse terminates. Depending on the current sensing
source impedance, a series input resistor may be required due to the delay between the internal logic and the turn off of the external
Output of the sample and hold buffer amplifier that captures and averages the CS signal. With a nominal 4x multiplier and the ability
to scale the signal externally with a resistor divider, the average current limit can be set independently of the peak current limit.
FN7654 Rev 0.00
January 31, 2011
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