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DATASHEET
ISL70040SEH, ISL73040SEH
Radiation Hardened Low-Side GaN FET Driver
The ISL70040SEH and ISL73040SEH are low-side
drivers designed to drive enhancement mode Gallium
Nitride (GaN) FETs in isolated topologies and boost type
configurations. The ISL70040SEH operates with a
supply voltage from 4.5V to 13.2V and has both
inverting (INB) and non-inverting (IN) inputs to satisfy
requirements for inverting and non-inverting gate drives
with a single device.
The ISL70040SEH and ISL73040SEH have a 4.5V gate
drive voltage (VDRV) generated using an internal
regulator that prevents the gate voltage from exceeding
the maximum gate-source rating of enhancement mode
GaN FETs. The gate drive voltage also features an
Undervoltage Lockout (UVLO) protection that ignores
the inputs (IN/INB) and keeps OUTL turned on to ensure
the GaN FET is in an OFF state whenever VDRV is below
the UVLO threshold.
The ISL70040SEH and ISL73040SEH inputs can
withstand voltages up to 14.7V regardless of the VDD
voltage. This allows the ISL70040SEH and
ISL73040SEH inputs to be connected directly to most
PWM controllers. The ISL70040SEH and ISL73040SEH
split outputs offer the flexibility to adjust the turn-on and
turn-off speed independently by adding additional
impedance to the turn-on/off paths.
The ISL70040SEH and ISL73040SEH operate across
the military temperature range from -55°C to +125°C
and are offered in an 8 Ld hermetically sealed ceramic
Surface Mount Device (SMD) package or die form.
Related Literature
For a full list of related documents, visit our website:
ISL70040SEH and ISL73040SEH device pages
FN8984
Rev.7.00
Jan 30, 2019
Features
• Wide operating voltage range of 4.5V to 13.2V
• Up to 14.7V logic inputs (regardless of VDD level)
• Inverting and non-inverting inputs
• Optimized to drive enhancement mode GaN FETs
• Internal 4.5V regulated gate drive voltage
• Independent outputs for adjustable
turn-on/turn-off speeds
• Full military temperature range operation
• TA = -55°C to +125°C
• TJ = -55°C to +150°C
• Radiation hardness assurance (wafer-by-wafer)
• High Dose Rate (HDR) (50-300rad(Si)/s):
100krad(Si) (ISL70040SEH only)
• Low Dose Rate (LDR) (0.01rad(Si)/s): 75krad(Si)
• SEE hardness (see the ISL70040SEH, ISL73040SEH
SEE Report for details)
• No SEB/L LETTH, VDD = 14.7V: 86MeV•cm2/mg
• No SET, LETTH, VDD = 13.2V: 86MeV•cm2/mg
• Electrically screened to DLA SMD 5962-17233
Applications
• Flyback and forward converters
• Boost and PFC converters
• Secondary synchronous FET drivers
22V - 36V
12V
12V
PWM
Controller
ISL7884xSEH
IS-1825BSEH
1 VDD
2 IN
3 INB
4 VSS
VDRV 8
OUTH 7
OUTL 6
VSSP 5
ISL70040SEH/
ISL73040SEH
ISL70023SEH
100V GaN FET
Figure 1. ISL70040SEH/ISL73040SEH 8 Ld SMD Package
4.8
4.7
-55°C
+25°C
4.6
4.5
4.4 +125°C
4.3
4.2
4 5 6 7 8 9 10 11 12 13 14
VDD (V)
Figure 2. VDRV Line Regulation vs Temperature
FN8984 Rev.7.00
Jan 30, 2019
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ISL70040SEH, ISL73040SEH
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Gate Drive for N-Channel GaN FETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Input Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Enable Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Power Dissipation of the Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 General PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. Die and Assembly Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Bond Pad Coordinates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8984 Rev.7.00
Jan 30, 2019
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ISL70040SEH, ISL73040SEH
1. Overview
1.1
VIN+
Typical Application Schematic
R8 C10
CR1
L1
ISL70024SEH
C1 Q 1
R4
R1 R2
VIN+
C4
C11
U1
VDD VDRV
IN OUTH
INB OUTL
VSS VSSP
ISL70040SEH
1. Overview
+
C2
C3
+VOUT
C12
C9
R5
C7 R3
R7 C8
R6
U2
VIN+
C6
C5
Figure 3. ISL70040SEH and ISL73040SEH Typical Application Schematic
1.2 Functional Block Diagram
9''
/LQHDU
5HJXODWRU
89/2
9'59
9'59
,1%
9663
287+
287/
,1 9'59
966
FN8984 Rev.7.00
Jan 30, 2019
9663
Figure 4. Block Diagram
9663
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ISL70040SEH, ISL73040SEH
1. Overview
1.3 Ordering Information
Ordering SMD Number
(Note 1)
Part Number
(Note 2)
Radiation Hardness
(Total Ionizing Dose)
HDR
LDR
Temperature
Range (°C)
Package
(RoHS
Compliant)
Package
Drawing
5962R1723301VXC ISL70040SEHVL
100krad(Si) 75krad(Si) -55 to +125 8 Ld SMD
J8.A
5962R1723301V9A ISL70040SEHVX
100krad(Si) 75krad(Si) -55 to +125 Die
-
N/A
ISL70040SEHL/PROTO (Note 3)
-
- -55 to +125 8 Ld SMD
J8.A
N/A
ISL70040SEHX/SAMPLE (Note 3)
-
- -55 to +125 Die
-
5962L1723302VXC ISL73040SEHVL
- 75krad(Si) -55 to +125 8 Ld SMD
J8.A
5962L1723302V9A ISL73040SEHVX
- 75krad(Si) -55 to +125 Die
-
N/A
ISL73040SEHL/PROTO (Note 3)
-
- -55 to +125 8 Ld SMD
J8.A
N/A
ISL73040SEHX/SAMPLE (Note 3)
-
- -55 to +125 Die
-
N/A
ISL70040SEHEV2Z (Note 4)
Evaluation Board with ISL70040SEH/ISL70023SEH
N/A
ISL70040SEHEV3Z (Note 4)
Evaluation Board with ISL70040SEH/ISL70024SEH
N/A
ISL73040SEHEV4Z (Note 4)
Half Bridge Power Stage using the ISL73040SEH, ISL73024SEH, and
the ISL71610M
Notes:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed must be used when ordering.
2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These
parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the
temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable
of meeting the electrical limits and conditions specified in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive
100% screening across the temperature range to the DLA SMD electrical limits. These part types do not come with a certificate of
conformance because there is no radiation assurance testing and they are not DLA qualified devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event
Effect (SEE) immunity.
Part Number
ISL70040SEH
ISL73040SEH
Table 1. Key Differences Between Family of Parts
Differences Between Parts
HDR to 100krad(Si)
LDR to 75krad(Si)
LDR to 75krad(Si)
FN8984 Rev.7.00
Jan 30, 2019
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ISL70040SEH, ISL73040SEH
1.4 Pin Configuration
8 Ld SMD
Top View
VDD 1
IN 2
INB 3
VSS 4
8 VDRV
7 OUTH
6 OUTL
5 VSSP
NOTE: The ESD triangular mark indicates Pin #1. It is a part of the device
marking and is placed on the lid in the quadrant where Pin #1 is located.
1. Overview
1.5 Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
N/A
Pin Name ESD Circuit
Description
VDD
3 Supply for the ISL70040SEH and ISL73040SEH internal linear regulator. Locally bypass
the supply to VDD using at least a 4.7µF ceramic capacitor.
IN 3 Non-inverting input pin which controls the OUTH and OUTL outputs. This input has
TTL/CMOS type thresholds. When using this device in an inverting application, tie this pin
to VDD to enable the outputs.
INB 3 Inverting input pin which controls the OUTH and OUTL outputs. This input has TTL/CMOS
type thresholds. When using this device in a non-inverting application, tie this pin to VSS to
enable the outputs.
VSS
4 Supply ground. Connect this pin to VSSP from the PCB ground plane.
VSSP
4 Power supply ground. Connect this pin to VSS from the PCB ground plane.
OUTL
2 Output low pin which is the gate driver turn-off output. Connect to the gate of the GaN FET
with a short, low inductance path. A series gate resistor can be used to adjust the turn-off
speed.
OUTH
1 Output high pin which is the gate driver turn-on output. Connect to the gate of the GaN FET
with a short, low inductance path. A series gate resistor can be used to adjust the turn-on
speed.
VDRV
1 Internal linear regulator output and the gate drive voltage. Locally bypass this pin using at
least a 4.7µF ceramic capacitor; 2µF to 10µF with variability.
LID N/A Internally connected to VSSP (Pin 5).
7V
VS
7V
VSS
PIN #
Circuit 1
PIN #
7V
VDRV
7V
7V
VSS
VSSP
Circuit 2
17V 17V
PIN #
VSS
VSSP
Circuit 3
VSS
VSSP
Circuit 4
FN8984 Rev.7.00
Jan 30, 2019
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