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DATASHEET
ISL62773
Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0
FN8263
Rev 1.00
Dec 16, 2015
The ISL62773 is fully compliant with AMD Fusion™ SVI 2.0 and
provides a complete solution for desktop microprocessor and
graphics processor core power. The ISL62773 controller supports
two Voltage Regulators (VRs) with three integrated gate drivers
and two optional external drivers for maximum flexibility. The
Core VR can be configured for 3-, 2-, or 1-phase operation while
the Northbridge VR supports 2- or 1-phase configurations. The two
VRs share a serial control bus to communicate with the AMD CPU
and achieve lower cost and smaller board area compared with
two-chip solutions.
The PWM modulator is based on Intersil’s Robust Ripple
Regulator R3™ technology. Compared to traditional modulators,
the R3 modulator can automatically change switching frequency
for faster transient settling time during load transients and
improved light-load efficiency.
The ISL62773 has several other key features. Both outputs
support DCR current sensing with a single NTC thermistor for
DCR temperature compensation or accurate resistor current
sensing. Both outputs utilize remote voltage sense, adjustable
switching frequency, OC protection and power-good.
Applications
• AMD Fusion CPU/GPU core power
• Desktop computers
Features
• Supports AMD SVI 2.0 serial data bus interface
- Serial VID clock frequency range 100kHz to 25MHz
• Dual output controller with integrated drivers
- Two dedicated core drivers
- One programmable driver for either core or Northbridge
• Precision voltage regulation
- 0.5% system accuracy over-temperature
- 0.5V to 1.55V in 6.25mV steps
- Enhanced load line accuracy
• Supports multiple current sensing methods
- Lossless inductor DCR current sensing
- Precision resistor current sensing
• Programmable 1-, 2- or 3-phase for the core output and 1- or
2-phase for the Northbridge output
• Adaptive body diode conduction time reduction
• Superior noise immunity and transient response
• Output current monitor and thermal monitor
• Differential remote voltage sensing
• High efficiency across entire load range
• Programmable slew rate, VID offset, droop and switching
frequency on both outputs
• OCP/WOC, OVP, PGOOD and thermal monitor
• Small footprint 48 Ld 6x6 QFN Package
- Pb-free (RoHS compliant)
Core Performance
100
90
80
70
60
50
40
30
20
10
0
0
VIN = 12V
VIN = 19V
VIN = 8V
VOUT CORE = 1.1V
5 10 15 20 25 30 35 40 45 50 55
IOUT (A)
FIGURE 1. EFFICIENCY vs LOAD
1.12
1.10
1.08
1.06
1.04
1.02
VIN = 12V
VIN = 8V
1.00
VIN = 19V
0.98 VOUT CORE = 1.1V
0.96 0 5 10 15 20 25 30 35 40 45 50 55
IOUT (A)
FIGURE 2. VOUT vs LOAD
FN8263 Rev 1.00
Dec 16, 2015
Page 1 of 37

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ISL62773
Table of Contents
Simplified Application Circuit for High Power CPU Core . . . 3
Simplified Application Circuit with 3 Internal Drivers Used
for Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Simplified Application Circuit for Mid-Power CPUs
[2+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simplified Application Circuit for Low Power CPUs
[1+1 Configuration] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Recommended Operating Conditions . . . . . . . . . . . . . . . . .11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .13
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Multiphase R3™ Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . 15
Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Voltage Regulation and Load Line Implementation . . . . . . . 16
Differential Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Adaptive Body Diode Conduction Time Reduction . . . . . . . . 20
Resistor Configuration Options. . . . . . . . . . . . . . . . . . . . . . .20
VR Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Floating DriverX and PWM_Y Configuration. . . . . . . . . . . . . . 21
VID-on-the-Fly Slew Rate Selection . . . . . . . . . . . . . . . . . . . . . 21
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AMD Serial VID Interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . 21
Pre-PWROK Metal VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SVI Interface Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VID-on-the-Fly Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SVI Data Communication Protocol . . . . . . . . . . . . . . . . . . . . . 22
SVI Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power States and Telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dynamic Load Line Slope Trim . . . . . . . . . . . . . . . . . . . . . . . . 26
Dynamic Offset Trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current-Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thermal Monitor [NTC, NTC_NB]. . . . . . . . . . . . . . . . . . . . . . . 27
Fault Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interface Pin Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . 28
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . 30
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Load Line Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal Monitor Component Selection . . . . . . . . . . . . . . . . . 32
Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FN8263 Rev 1.00
Dec 16, 2015
Page 2 of 37

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ISL62773
Simplified Application Circuit for High Power CPU Core
NB_PH1
NB_PH2
VNB1
VNB2
NB_PH1
NB_PH2
VNB_SENSE
VCORE_SENSE
PH1
PH2
PH3
VO1
VO2
VO3
Ri
Cn NTC
ISEN1_NB
ISEN2_NB
ISUMN_NB
ISUMP_NB
BOOTX
UGATEX
PHASEX
LGATEX
FCCM_NB
VIN
NB_PH1
VIN
VNB1
VNB
PWM2_NB
COMP_NB
FB_NB
VSEN_NB
PWROK
SVT
µP SVD
SVC
VDDIO
IMON_NB
NTC_NB
VR_HOT_L
IMON
NTC
PWM_Y
COMP
FB2
FB
VSEN
RTN
ISEN1
ISEN2
ISEN3
Ri
Cn NTC
ISUMN
ISUMP
ISL62773
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
NB_PH2
THERMAL INDICATOR
VIN
PH3
VIN
PH2
VIN
PH1
VNB2
VO3
VCORE
VO2
VO1
FN8263 Rev 1.00
Dec 16, 2015
FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
Page 3 of 37

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ISL62773
Simplified Application Circuit with 3 Internal Drivers Used for Core
VIN
NB_PH1
NB_PH2
VNB1
VNB2
NB_PH1
NB_PH2
VNB_SENSE
VCORE_SENSE
PH1
PH2
PH3
VO1
VO2
VO3
Ri
Cn NTC
ISEN1_NB
ISEN2_NB
ISUMN_NB
ISUMP_NB
PWM_Y
FCCM_NB
PWM2_NB
µP
Ri
Cn NTC
COMP_NB
FB_NB
VSEN_NB
PWROK
SVT
SVD
SVC
VDDIO
IMON_NB
NTC_NB
VR_HOT_L
IMON
NTC
BOOTX
UGATEX
PHASEX
COMP
FB2
FB
VSEN
RTN
ISEN1
ISEN2
ISEN3
ISUMN
ISUMP
ISL62773
LGATEX
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
NB_PH1
VIN
NB_PH2
THERMAL INDICATOR
VIN
PH3
VIN
PH2
VIN
PH1
VNB
VNB1
VNB2
V03
VCORE
VO2
VO1
FN8263 Rev 1.00
Dec 16, 2015
FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
Page 4 of 37

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ISL62773
Simplified Application Circuit for Mid-Power CPUs [2+1 Configuration]
* Resistor required or ISEN1_NB
will pull HIGH if left open and
disable Channel 1.
10kΩ*
NBN
NBP
+5V
Ri
NTC
Cn
ISEN1_NB
ISEN2_NB
ISUMN_NB
ISUMP_NB
PWM_Y
FCCM_NB
PWM2_NB OPEN
VIN
VNB
NBP
NBN
VNB_SENSE
VCORE_SENSE
VP1
VP2
VN1
VN2
µP
+5V
Ri
Cn NTC
COMP_NB
FB_NB
IMON_NB
NTC_NB
VSEN_NB
PWROK
SVT
SVD
SVC
VDDIO
BOOTX
UGATEX
PHASEX
LGATEX
VR_HOT_L
IMON
COMP
ISL62773
NTC
FB2
FB
VSEN
RTN
ISEN1
ISEN2
ISEN3
BOOT2
UGATE2
PHASE2
LGATE2
BOOT1
ISUMN
UGATE1
PHASE1
OPEN
OPEN
OPEN
OPEN
THERMAL INDICATOR
VIN
VP2
VIN
VN2
ISUMP
LGATE1
VP1 VN1
VCORE
FN8263 Rev 1.00
Dec 16, 2015
FIGURE 5. TYPICAL APPLICATION CIRCUIT USING RESISTOR SENSING
Page 5 of 37