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Low-Power CK420BQ Derivative for PCIe
Separate Clock Architectures
932SQL456
DATASHEET
General Description
The 932SQL456 is a low power version of the CK420BQ
synthesizer for Intel-based server platforms. It has 85 ohm
Low-Power (LP) HCSL outputs that save 48 resistors and
reduce power consumption by 50% compared to the standard
CK420BQ. The 932SQL456 is driven with a 25MHz crystal for
maximum performance. It generates CPU outputs of
100MHz. This device meets Separate- Reference-no-Spread
(SRnS) PCIe requirements making it ideal for use in systems
that need to communicate “outside the box”.
Recommended Application
Low-Power CK420BQ for SRnS PCIe Applications
Key Specifications
CPU, SRC, NS_SRC and NS_SAS cycle-cycle jitter <50ps
Output to output skew <50ps
Phase jitter: PCIe Gen2 SRnS <2.2ps rms
Phase jitter: PCIe Gen3 SRnS <0.7ps rms
Phase jitter: QPI <0.3ps rms
Phase jitter: NS-SAS <1.3ps rms using long period phase
jitter method
Pin Configurations
Features/Benefits
Integrated 85-ohm differential terminations; saves 48
resistors compared to CK420BQ
LP-HCSL outputs; up to 50% power savings compared to
standard CK420BQ
64-pin TSSOP and VFQFPN packages; smallest board
footprint
Available in -40° to +85°C industrial temperature range
version; supports demanding operating environments
Output Features
Differential outputs are LP-HCSL with integrated 85
terminations
11 – non-spreading interchangeable 100MHz differential
outputs
4 – “CPU” outputs
2 – “NS_SAS” outputs
2 – “NS_SRC” outputs
3 – “SRC” outputs
1 – DOT96 96MHz output
1 – 3.3V 48M output
5 – 3.3V PCI outputs
1 – 3.3V 14.318M output
SMBCLK 1
64 SMBDAT
GND14 2
63 VDDCPU
AVDD14 3
62 CPU3_Z85T
VDD14 4
61 CPU3_Z85C
vREF14_2x/TEST_SELLV 5
60 CPU2_Z85T
GND14 6
59 CPU2_Z85C
GNDXTAL 7
58 GNDCPU
X1_25 8
57 VDDCPU
X2_25 9
56 CPU1_Z85T
VDDXTAL 10
55 CPU1_Z85C
GNDPCI 11
54 CPU0_Z85T
VDDPCI 12
53 CPU0_Z85C
PCI4_2x 13
52 GNDNS
PCI3_2x 14
51 AVDD_NS_SAS
PCI2_2x 15
50 NS_SAS1_Z85T
PCI1_2x 16
49 NS_SAS1_Z85C
PCI0_2x 17
48 NS_SAS0_Z85T
GNDPCI 18
47 NS_SAS0_Z85C
VDDPCI 19
46 GNDNS
VDD48 20
45 VDDNS
48M_2x 21
44 NS_SRC1_Z85T
GND48 22
43 NS_SRC1_Z85C
GND96 23
42 NS_SRC0_Z85T
DOT96_Z85T 24
41 NS_SRC0_Z85C
DOT96_Z85C 25
40 NC
AVDD96 26
39 GNDSRC
TEST_MODE 27
38 AVDD_SRC
CKPWRGD#/PD 28
37 VDDSRC
VDDSRC 29
36 SRC2_Z85T
SRC0_Z85T 30
35 SRC2_Z85C
SRC0_Z85C 31
34 SRC1_Z85T
GNDSRC 32
33 SRC1_Z85C
64-TSSOP
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
932SQL456 REVISION B 09/29/15
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GNDPCI 1
VDDPCI 2
48 GNDCPU
47 VDDCPU
PCI4_2x 3
46 CPU1_Z85T
PCI3_2x 4
PCI2_2x 5
45 CPU1_Z85C
44 CPU0_Z85T
PCI1_2x 6
43 CPU0_Z85C
PCI0_2x 7
GNDPCI 8
VDDPCI 9
VDD48 10
932SQL456
epad = pin 65,
connect to GND
42 GNDNS
41 AVDD_NS_SAS
40 NS_SAS1_Z85T
39 NS_SAS1_Z85C
48M_2x 11
GND48 12
38 NS_SAS0_Z85T
37 NS_SAS0_Z85C
GND96 13
36 GNDNS
DOT96_Z85T 14
DOT96_Z85C 15
35 VDDNS
34 NS_SRC1_Z85T
AVDD96 16
33 NS_SRC1_Z85C
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Pin VFQFPN
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
1 ©2015 Integrated Device Technology, Inc.

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932SQL456 DATASHEET
64TSSOP Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIN NAME
SMBCLK
GND14
AVDD14
VDD14
vREF14_2x/TEST_SELLV
GND14
GNDXTAL
X1_25
X2_25
VDDXTAL
GNDPCI
VDDPCI
PCI4_2x
PCI3_2x
PCI2_2x
PCI1_2x
PCI0_2x
GNDPCI
VDDPCI
VDD48
48M_2x
GND48
GND96
DOT96_Z85T
DOT96_Z85C
AVDD96
TEST_MODE
CKPWRGD#/PD
VDDSRC
SRC0_Z85T
SRC0_Z85C
GNDSRC
SRC1_Z85C
SRC1_Z85T
SRC2_Z85C
SRC2_Z85T
VDDSRC
AVDD_SRC
GNDSRC
NC
TYPE
DESCRIPTION
IN Clock pin of SMBUS circuitry, 5V tolerant
PWR Ground pin for 14MHz output and logic.
PWR Analog power pin for 14MHz PLL
PWR Power pin for 14MHz output and logic
14.318 MHz reference clock capable of driving 2 loads/ TEST_SEL latched input to enable test
I/O mode. The TEST_SEL input is a low threshold input. See the Electrical Tables and the Test
Clarification Table. This pin has a weak (~120Kohm) internal pull down.
PWR Ground pin for 14MHz output and logic.
PWR Ground pin for Crystal Oscillator.
IN Crystal input, Nominally 25.00MHz.
OUT Crystal output, Nominally 25.00MHz.
PWR 3.3V power for the crystal oscillator.
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
PWR 3.3V power for the 48MHz output and logic
OUT 3.3V 48MHz output
PWR Ground pin for 48MHz output and logic.
PWR Ground pin for DOT96 output and logic.
OUT True clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential 96MHz output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
IN Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
PWR 3.3V power for the SRC outputs and logic
OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR Ground pin for SRC outputs and logic.
OUT
Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm
transmission lines with no external components.
PWR 3.3V power for the SRC outputs and logic
PWR 3.3V power for the SRC PLL analog circuits
PWR Ground pin for SRC outputs and logic.
N/A No Connection.
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES
2
REVISION B 09/29/15

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932SQL456 DATASHEET
64TSSOP Pin Descriptions (cont.)
PIN #
PIN NAME
41 NS_SRC0_Z85C
42 NS_SRC0_Z85T
43 NS_SRC1_Z85C
44 NS_SRC1_Z85T
45 VDDNS
46 GNDNS
47 NS_SAS0_Z85C
48 NS_SAS0_Z85T
49 NS_SAS1_Z85C
50 NS_SAS1_Z85T
51 AVDD_NS_SAS
52 GNDNS
53 CPU0_Z85C
54 CPU0_Z85T
55 CPU1_Z85C
56 CPU1_Z85T
57 VDDCPU
58 GNDCPU
59 CPU2_Z85C
60 CPU2_Z85T
61 CPU3_Z85C
62 CPU3_Z85T
63 VDDCPU
64 SMBDAT
TYPE
DESCRIPTION
OUT Complementary clock of low-power push-pull differential non-spreading SRC output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the Non-Spreading differential outputs outputs and logic
PWR Ground pin for non-spreading differential outputs and logic.
OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits.
PWR Ground pin for non-spreading differential outputs and logic.
OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential CPU output.
drive 85ohm transmission lines with no external components.
Internally terminated to
OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm
transmission lines with no external components.
PWR 3.3V power for the CPU outputs and logic
PWR Ground pin for CPU outputs and logic.
OUT
Complementary clock of low-power push-pull differential CPU output.
drive 85ohm transmission lines with no external components.
Internally terminated to
OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm
transmission lines with no external components.
PWR 3.3V power for the CPU outputs and logic
I/O Data pin of SMBUS circuitry, 5V tolerant
REVISION B 09/29/15
3 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES

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932SQL456 DATASHEET
64VFQFPN Pin Descriptions
PIN #
PIN NAME
1 GNDPCI
2 VDDPCI
3 PCI4_2x
4 PCI3_2x
5 PCI2_2x
6 PCI1_2x
7 PCI0_2x
8 GNDPCI
9 VDDPCI
10 VDD48
11 48M_2x
12 GND48
13 GND96
14 DOT96_Z85T
15 DOT96_Z85C
16 AVDD96
17 TEST_MODE
18 CKPWRGD#/PD
19 VDDSRC
20 SRC0_Z85T
21 SRC0_Z85C
22 GNDSRC
23 SRC1_Z85C
24 SRC1_Z85T
25 SRC2_Z85C
26 SRC2_Z85T
27 VDDSRC
28 AVDD_SRC
29 GNDSRC
30 NC
31 NS_SRC0_Z85C
32 NS_SRC0_Z85T
33 NS_SRC1_Z85C
34 NS_SRC1_Z85T
35 VDDNS
36 GNDNS
37 NS_SAS0_Z85C
38 NS_SAS0_Z85T
TYPE
DESCRIPTION
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
OUT 3.3V PCI clock output
PWR Ground pin for PCI outputs and logic.
PWR 3.3V power for the PCI outputs and logic
PWR 3.3V power for the 48MHz output and logic
OUT 3.3V 48MHz output
PWR Ground pin for 48MHz output and logic.
PWR Ground pin for DOT96 output and logic.
OUT
True clock of low-power push-pull differential 96MHz output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential 96MHz output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the 48/96MHz PLL and the 96MHz output and logic
IN TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
IN Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
PWR 3.3V power for the SRC outputs and logic
OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR Ground pin for SRC outputs and logic.
OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm
transmission lines with no external components.
OUT Complementary clock of low-power push-pull differential SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential SRC output. Internally terminated to drive 85ohm
transmission lines with no external components.
PWR 3.3V power for the SRC outputs and logic
PWR 3.3V power for the SRC PLL analog circuits
PWR Ground pin for SRC outputs and logic.
N/A No Connection.
OUT Complementary clock of low-power push-pull differential non-spreading SRC output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
OUT
Complementary clock of low-power push-pull differential non-spreading SRC output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SRC output. Internally terminated to
drive 85ohm transmission lines with no external components.
PWR 3.3V power for the Non-Spreading differential outputs outputs and logic
PWR Ground pin for non-spreading differential outputs and logic.
OUT
Complementary clock of low-power push-pull differential non-spreading SAS output. Internally
terminated to drive 85ohm transmission lines with no external components.
OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to
drive 85ohm transmission lines with no external components.
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES
4
REVISION B 09/29/15

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932SQL456 DATASHEET
64VFQFPN Pin Descriptions (cont.)
PIN #
PIN NAME
TYPE
DESCRIPTION
39 NS_SAS1_Z85C
OUT Complementary clock of low-power push-pull differential non-spreading SAS output. Internally
terminated to drive 85ohm transmission lines with no external components.
40 NS_SAS1_Z85T
OUT True clock of low-power push-pull differential non-spreading SAS output. Internally terminated to
drive 85ohm transmission lines with no external components.
41 AVDD_NS_SAS
PWR 3.3V power for the non-spreading SAS/SRC PLL analog circuits.
42 GNDNS
PWR Ground pin for non-spreading differential outputs and logic.
43 CPU0_Z85C
OUT
Complementary clock of low-power push-pull differential CPU output.
drive 85ohm transmission lines with no external components.
Internally terminated to
44 CPU0_Z85T
OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm
transmission lines with no external components.
45 CPU1_Z85C
OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to
drive 85ohm transmission lines with no external components.
46 CPU1_Z85T
OUT
True clock of low-power push-pull differential CPU output.
transmission lines with no external components.
Internally terminated to drive 85ohm
47 VDDCPU
PWR 3.3V power for the CPU outputs and logic
48 GNDCPU
PWR Ground pin for CPU outputs and logic.
49 CPU2_Z85C
OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to
drive 85ohm transmission lines with no external components.
50 CPU2_Z85T
OUT
True clock of low-power push-pull differential CPU output.
transmission lines with no external components.
Internally terminated to drive 85ohm
51 CPU3_Z85C
OUT Complementary clock of low-power push-pull differential CPU output. Internally terminated to
drive 85ohm transmission lines with no external components.
52 CPU3_Z85T
OUT True clock of low-power push-pull differential CPU output. Internally terminated to drive 85ohm
transmission lines with no external components.
53 VDDCPU
PWR 3.3V power for the CPU outputs and logic
54 SMBDAT
I/O Data pin of SMBUS circuitry, 5V tolerant
55 SMBCLK
IN Clock pin of SMBUS circuitry, 5V tolerant
56 GND14
PWR Ground pin for 14MHz output and logic.
57 AVDD14
PWR Analog power pin for 14MHz PLL
58 VDD14
PWR Power pin for 14MHz output and logic
14.318 MHz reference clock capable of driving 2 loads/ TEST_SEL latched input to enable test
59 vREF14_2x/TEST_SELLV I/O mode. The TEST_SEL input is a low threshold input. See the Electrical Tables and the Test
Clarification Table. This pin has a weak (~120Kohm) internal pull down.
60 GND14
PWR Ground pin for 14MHz output and logic.
61 GNDXTAL
PWR Ground pin for Crystal Oscillator.
62 X1_25
IN Crystal input, Nominally 25.00MHz.
63 X2_25
OUT Crystal output, Nominally 25.00MHz.
64 VDDXTAL
PWR 3.3V power for the crystal oscillator.
65 EPAD
GND Epad should be connected to ground.
REVISION B 09/29/15
5 LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES