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Rev. 1.6, Jan. 2017
K4A4G045WE
K4A4G085WE
4Gb E-die DDR4 SDRAM
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
1.2V
datasheet
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K4A4G045WE
K4A4G085WE
datasheet
Revision History
Revision No.
1.0
1.01
1.1
1.2
1.3
1.4
1.5
1.51
1.6
History
- First SPEC release
- Correction of typo
- Added values on page 11 [Table 5]
- Addition of Industrial temp
- Addition of DDR4-2666
- Addition of IDD Current specification of 2666Mbps
- Addition of DDR4-2666 (x4)
- Change of Package pinout on page 5
- Update referring to JEDEC DDR4 datasheet rev.79-4B
Rev. 1.6
DDR4 SDRAM
Draft Date
4th Jun, 2015
11th Aug, 2015
27th Oct, 2015
11th Apr, 2016
22th Jun, 2016
3rd Aug, 2016
22th Aug, 2016
4th Nov, 2016
12th Jan, 2017
Remark
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Editor
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
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K4A4G045WE
K4A4G085WE
datasheet
Rev. 1.6
DDR4 SDRAM
Table Of Contents
4Gb E-die DDR4 SDRAM
1. Ordering Information .....................................................................................................................................................5
2. Key Features.................................................................................................................................................................5
3. Package pinout/Mechanical Dimension & Addressing..................................................................................................6
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7
3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8
4. Input/Output Functional Description..............................................................................................................................9
5. DDR4 SDRAM Addressing ...........................................................................................................................................11
6. Absolute Maximum Ratings ..........................................................................................................................................12
6.1 Absolute Maximum DC Ratings............................................................................................................................... 12
6.2 DRAM Component Operating Temperature Range ................................................................................................ 12
7. AC & DC Operating Conditions.....................................................................................................................................12
8. AC & DC Input Measurement Levels ............................................................................................................................13
8.1 AC & DC Logic Input Levels for Single-ended Signals ............................................................................................ 13
8.2 AC and DC Input Measurement Levels: VREF Tolerances..................................................................................... 13
8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 14
8.3.1. Differential Signals Definition ........................................................................................................................... 14
8.3.2. Differential Swing Requirement for Clock (CK_t - CK_c) ................................................................................. 14
8.3.3. Single-ended Requirements for Differential Signals ........................................................................................ 15
8.3.4. Address, Command and Control Overshoot and Undershoot Specifications................................................... 16
8.3.5. Clock Overshoot and Undershoot Specifications ............................................................................................. 17
8.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications ................................................................. 18
8.4 Slew Rate Definitions .............................................................................................................................................. 19
8.4.1. Slew Rate Definitions for Differential Input Signals (CK) ................................................................................. 19
8.4.2. Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ).................................................................. 20
8.5 Differential Input Cross Point Voltage...................................................................................................................... 21
8.6 CMOS Rail to Rail Input Levels ............................................................................................................................... 22
8.6.1. CMOS Rail to Rail Input Levels for RESET_n ................................................................................................. 22
8.7 AC and DC Logic Input Levels for DQS Signals...................................................................................................... 23
8.7.1. Differential Signal Definition ............................................................................................................................. 23
8.7.2. Differential Swing Requirements for DQS (DQS_t - DQS_c) ........................................................................... 23
8.7.3. Peak Voltage Calculation Method .................................................................................................................... 24
8.7.4. Differential Input Cross Point Voltage .............................................................................................................. 25
8.7.5. Differential Input Slew Rate Definition.............................................................................................................. 26
9. AC and DC Output Measurement Levels......................................................................................................................27
9.1 Output Driver DC Electrical Characteristics............................................................................................................. 27
9.1.1. Alert_n Output Drive Characteristic.................................................................................................................. 29
9.1.2. Output Driver Characteristic of Connectivity Test ( CT ) Mode ........................................................................ 29
9.2 Single-ended AC & DC Output Levels..................................................................................................................... 30
9.3 Differential AC & DC Output Levels......................................................................................................................... 30
9.4 Single-ended Output Slew Rate .............................................................................................................................. 31
9.5 Differential Output Slew Rate .................................................................................................................................. 32
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode .......................................................................... 33
9.7 Test Load for Connectivity Test Mode Timing ......................................................................................................... 33
10. Speed Bin ...................................................................................................................................................................34
10.1 Speed Bin Table Note ........................................................................................................................................... 39
11. IDD and IDDQ Specification Parameters and Test Conditions ...................................................................................40
11.1 IDD, IPP and IDDQ Measurement Conditions....................................................................................................... 40
11.2 4Gb DDR4 SDRAM E-die IDD Specification Table ............................................................................................... 55
12. Input/Output Capacitance ...........................................................................................................................................57
13. Electrical Characteristics & AC Timing .......................................................................................................................59
13.1 Reference Load for AC Timing and Output Slew Rate .......................................................................................... 59
13.2 tREFI ..................................................................................................................................................................... 59
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K4A4G045WE
K4A4G085WE
datasheet
Rev. 1.6
DDR4 SDRAM
13.3 Clock Specification ................................................................................................................................................ 60
13.3.1. Definition for tCK(abs) .................................................................................................................................... 60
13.3.2. Definition for tCK(avg) .................................................................................................................................... 60
13.3.3. Definition for tCH(avg) and tCL(avg) ............................................................................................................. 60
13.3.4. Definition for tERR(nper) ................................................................................................................................ 60
13.4 Timing Parameters by Speed Grade ..................................................................................................................... 61
13.5 Rounding Algorithms ............................................................................................................................................ 67
13.6 The DQ Input Receiver Compliance Mask for Voltage and Timing ....................................................................... 68
13.7 DDR4 Function Matrix ........................................................................................................................................... 72
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K4A4G045WE
K4A4G085WE
datasheet
Rev. 1.6
DDR4 SDRAM
1. Ordering Information
[ Table 1 ] Samsung 4Gb DDR4 E-die ordering information table
Organization
DDR4-2133 (15-15-15)
1Gx4
K4A4G045WE-BCPB
512Mx8
K4A4G085WE-BCPB
512Mx8
K4A4G085WE-BIPB
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward compatible to lower frequency
3. 13th digit stands for below.
"C" : Commercial temp/Normal power
"I" : Industrial temp/Normal power
DDR4-2400 (17-17-17)
K4A4G045WE-BCRC
K4A4G085WE-BCRC
K4A4G085WE-BIRC
2. Key Features
DDR4-2666 (19-19-19)2
K4A4G045WE-BCTD
K4A4G085WE-BCTD
K4A4G085WE-BITD
Package
78 FBGA
78 FBGA
78 FBGA
[ Table 2 ] 4Gb DDR4 E-die Speed bins
Speed
DDR4-1600
11-11-11
tCK(min)
1.25
CAS Latency
11
tRCD(min)
13.75
tRP(min)
13.75
tRAS(min)
35
tRC(min)
48.75
DDR4-1866
13-13-13
1.071
13
13.92
13.92
34
47.92
DDR4-2133
15-15-15
0.938
15
14.06
14.06
33
47.06
DDR4-2400
17-17-17
0.833
17
14.16
14.16
32
46.16
DDR4-2666
19-19-19
0.75
19
14.25
14.25
32
46.25
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.2V (1.14V~1.26V)
• VDDQ = 1.2V (1.14V~1.26V)
• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin,
1067MHz fCK for 2133Mb/sec/pin, 1200MHz fCK for 2400Mb/sec/pin,
1333MHz fCK for2666Mb/sec/pin
• 16 Banks (4 Bank Groups)
• Programmable CAS Latency (posted CAS):
10,11,12,13,14,15,16,17,18
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12
(DDR4-1866),11,14 (DDR4-2133),12,16 (DDR4-2400) and 14,18
(DDR4-2666)
• 8-bit pre-fetch
• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read
or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal (self) calibration: Internal self calibration through ZQ pin
(RZQ: 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at
85C < TCASE < 95 C
• Support Industrial Temp (-4095C)
- tREFI 7.8us at -40 °C TCASE 85°C
- tREFI 3.9us at 85 °C < TCASE 95°C
• Asynchronous Reset
• Package: 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
• CRC (Cyclic Redundancy Check) for Read/Write data security
• Command address parity check
• DBI (Data Bus Inversion)
• Gear down mode
• POD (Pseudo Open Drain) interface for data input/output
• Internal VREF for data inputs
• External VPP for DRAM Activating Power
• PPR and sPPR is supported
The 4Gb DDR4 SDRAM E-die is organized as a 64Mbit x 4 I/Os x 16banks
or 32Mbit x8 I/Os x 16banks device. This synchronous device achieves
high speed double-data-rate transfer rates of up to 2666Mb/sec/pin (DDR4-
2666) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR4 device operates
with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V).
The 4Gb DDR4 E-die device is available in 78ball FBGAs(x4/x8).
NOTE: 1. This data sheet is an abstract of full DDR4 specification and does not cover the common features which are described in “DDR4 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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