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DATASHEET
ISL6333, ISL6333A, ISL6333B, ISL6333C
Three-Phase Buck PWM Controller with Integrated MOSFET Drivers and Light
Load Efficiency Enhancements for Intel VR11.1 Applications
FN6520
Rev 3.00
Oct 8, 2010
The ISL6333 three-phase PWM family of control ICs provide a
precision voltage regulation system for advanced
microprocessors. The integration of power MOSFET drivers
into the controller IC marks a departure from the separate PWM
controller and driver configuration of previous multi-phase
product families. By reducing the number of external parts, this
integration is optimized for a cost and space saving power
management solution.
The ISL6333 controllers are designed to be compatible with
Intel VR11.1 Applications. Features that make these controllers
compatible include an IMON pin for output current monitoring,
and a Power State Indicator (PSI#) pin for phase dropping and
higher efficiency during light load states. An 8-bit VID input is
used to select the desired output voltage from the VR11 DAC
table. A circuit is provided for remote voltage sensing,
compensating for any potential difference between remote and
local grounds. The output voltage can also be positively or
negatively offset through the use of a single external resistor.
The ISL6333 controllers also include advanced control loop
features for optimal transient response to load application and
removal. One of these features is highly accurate, fully
differential, continuous DCR current sensing for load line
programming and channel current balance. Active Pulse
Positioning (APP) Modulation and Adaptive Phase Alignment
(APA) are two other unique features, allowing for quicker initial
response to high di/dt load transients. With this quicker initial
response to load transients, the number of output bulk
capacitors can be reduced, helping to reduce cost.
Integrated into the ISL6333 controllers are user-programmable
current sense resistors, which require only a single external
resistor to set their values. No external current sense resistors
are required. Another unique feature of the ISL6333 controllers
is the addition of a dynamic VID compensation pin that allows
optimizing compensation to be added for well-controlled
dynamic VID response.
Protection features of these controller ICs include a set of
sophisticated overvoltage, undervoltage, and overcurrent
protection. Furthermore, the ISL6333 controllers include
protection against an open circuit on the remote sensing inputs.
Combined, these features provide advanced protection for the
microprocessor and power system.
Features
• Intel VR11.1 Compatible
- IMON Pin for Output Current Monitoring
- Power State Indicator (PSI#) Pin for Phase Dropping
and Higher Efficiency During Light Load States
• CPURST_N Input to Eliminate Required Extensive
External Circuit for proper PSI# Operation of Intel’s
Eaglelake Chipset Platform (ISL6333B, ISL6333C Only)
• Integrated Multi-Phase Power Conversion
- 3-Phase or 2-Phase Operation with Internal Drivers
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
• Optimal Transient Response
- Active Pulse Positioning (APP) Modulation
- Adaptive Phase Alignment (APA)
• Fully Differential, Continuous DCR Current Sensing
- Integrated Programmable Current Sense Resistors
- Accurate Load Line Programming
- Precision Channel Current Balancing
• Gate Voltage Optimization Technology (ISL6333,
ISL6333B Only)
• Power Saving Diode Emulation Mode (ISL6333, ISL6333B
Only)
• Optimized for use with Coupled Inductors
• Variable Gate Drive Bias: +5V to +12V
• Microprocessor Voltage Identification Inputs
- 8-bit VID Input for Selecting VR11 DAC Voltages
- Dynamic VID Technology
• Dynamic VID Compensation
• Overcurrent Protection and Channel Current Limit
• Multi-tiered Overvoltage Protection
• Digital Soft-Start
• Selectable Operation Frequency up to 1.0MHz Per Phase
• Pb-free (RoHS Compliant)
FN6520 Rev 3.00
Oct 8, 2010
Page 1 of 40

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ISL6333, ISL6333A, ISL6333B, ISL6333C
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6333CRZ*
ISL6333 CRZ
0 to +70
48 Ld 7x7 QFN
L48.7x7
ISL6333IRZ*
ISL6333 IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
ISL6333ACRZ*
ISL6333A CRZ
0 to +70
48 Ld 7x7 QFN
L48.7x7
ISL6333AIRZ*
ISL6333A IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
ISL6333BCRZ*
ISL6333B CRZ
0 to +70
48 Ld 7x7 QFN
L48.7x7
ISL6333BIRZ*
ISL6333B IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
ISL6333CCRZ*
ISL6333C CRZ
0 to +70
48 Ld 7x7 QFN
L48.7x7
ISL6333CIRZ*
ISL6333C IRZ
-40 to +85
48 Ld 7x7 QFN
L48.7x7
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
Pinouts
ISL6333 (48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
RSET 1
OFS 2
FS 3
SS 4
VCC 5
REF 6
APA 7
COMP 8
DVC 9
FB 10
IDROOP 11
VDIFF 12
GND (PIN 49)
36 VR_RDY
35 EN
34 PUVCC
33 PHASE2
32 UGATE2
31 BOOT2
30 LGATE2
29 PVCC2_3
28 LGATE3
27 BOOT3
26 UGATE3
25 PHASE3
13 14 15 16 17 18 19 20 21 22 23 24
FN6520 Rev 3.00
Oct 8, 2010
Page 2 of 40

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ISL6333, ISL6333A, ISL6333B, ISL6333C
Pinouts (Continued)
ISL6333A (48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
RSET 1
OFS 2
FS 3
SS 4
VCC 5
REF 6
APA 7
COMP 8
DVC 9
FB 10
IDROOP 11
VDIFF 12
GND (PIN 49)
36 VR_RDY
35 EN
34 PUVCC
33 PHASE2
32 UGATE2
31 BOOT2
30 LGATE2
29 PVCC3
28 LGATE3
27 BOOT3
26 UGATE3
25 PHASE3
13 14 15 16 17 18 19 20 21 22 23 24
ISL6333B (48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
RSET 1
OFS 2
FS 3
SS 4
VCC 5
REF 6
APA 7
COMP 8
DVC 9
FB 10
CPURST_N 11
VDIFF 12
GND (PIN 49)
36 VR_RDY
35 EN
34 PUVCC
33 PHASE2
32 UGATE2
31 BOOT2
30 LGATE2
29 PVCC2_3
28 LGATE3
27 BOOT3
26 UGATE3
25 PHASE3
13 14 15 16 17 18 19 20 21 22 23 24
FN6520 Rev 3.00
Oct 8, 2010
Page 3 of 40

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ISL6333, ISL6333A, ISL6333B, ISL6333C
Pinouts (Continued)
ISL6333C (48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
RSET 1
OFS 2
FS 3
SS 4
VCC 5
REF 6
APA 7
COMP 8
DVC 9
FB 10
CPURST_N 11
VDIFF 12
GND (PIN 49)
36 VR_RDY
35 EN
34 PUVCC
33 PHASE2
32 UGATE2
31 BOOT2
30 LGATE2
29 PVCC3
28 LGATE3
27 BOOT3
26 UGATE3
25 PHASE3
13 14 15 16 17 18 19 20 21 22 23 24
Controller Descriptions and Comments
CONTROLLER
DIODE
EMULATION
MODE (DEM)
GATE VOLTAGE OPTIMIZATION
TECHNOLOGY
(GVOT)
DROOP PIN
ENABLE/DISABLE DROOP
CPURST_N PIN
ISL6333
YES
YES
YES
Enable/Disable
NO
ISL6333A
NO
NO
YES
Enable/Disable
NO
ISL6333B
YES
YES
NO Always Enabled
YES
ISL6333C
NO
NO
NO Always Enabled
YES
CONTROLLER
COMMENTS
ISL6333
When PSI# is set high, the controller operates normally in continuous conduction mode (CCM) with all active channels firing.
When the PSI# pin is set low, the controller transitions to single phase operation and changes to diode emulation mode (DEM).
The controller also utilizes it’s new Gate Voltage Optimization Technology (GVOT) to reduce Channel 1’s lower MOSFET gate
drive voltage. This controller yields the highest low load efficiency.
ISL6333A
When PSI# is set high, the controller operates normally in continuous conduction mode (CCM) with all active channels firing.
When the PSI# pin is set low, the controller transitions to single phase operation only.
ISL6333B
Same feature set as the ISL6333 controller with two additional changes. The CPURST_N pin is added to eliminate extensive
external circuitry required for proper PSI# operation of Intel’s Eaglelake Chipset Platform. The droop pin has been removed
and the droop current now flows out of the FB pin. The droop feature is always active. This controller yields the highest low
load efficiency.
ISL6333C
Same feature set as the ISL6333A controller with two additional changes. The CPURST_N pin is added to eliminate extensive
external circuitry required for proper PSI# operation of Intel’s Eaglelake Chipset Platform. The droop pin has been removed
and the droop current now flows out of the FB pin. The droop feature is always active.
FN6520 Rev 3.00
Oct 8, 2010
Page 4 of 40

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ISL6333, ISL6333A, ISL6333B, ISL6333C
Integrated Driver Block Diagram
LVCC UVCC
PWM
LOW POWER
STATE
SOFT-START
AND
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
BOOT
UGATE
20k
PHASE
10k
LGATE
FN6520 Rev 3.00
Oct 8, 2010
Page 5 of 40