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DATASHEET

X5323, X5325 (Replaces X25323, X25325)

CPU Supervisor with 32kBit SPI EEPROM

FN8131

Rev 3.00

December 9, 2015

These devices combine four popular functions, Power-on

Reset Control, Watchdog Timer, Supply Voltage Supervision,

and Block Lock Protect Serial EEPROM Memory in one

package. This combination lowers system cost, reduces

board space requirements, and increases reliability.

Applying power to the device activates the power-on reset

circuit which holds RESET/RESET active for a period of

time. This allows the power supply and oscillator to stabilize

before the processor can execute code.

The Watchdog Timer provides an independent protection

mechanism for microcontrollers. When the microcontroller

fails to restart a timer within a selectable time out interval,

the device activates the RESET/RESET signal. The user

selects the interval from three preset values. Once selected,

the interval does not change, even after cycling the power.

The device’s low VCC detection circuitry protects the user’s

system from low voltage conditions, resetting the system

when VCC falls below the minimum VCC trip point.

RESET/RESET is asserted until VCC returns to proper

operating level and stabilizes. Five industry standard VTRIP

thresholds are available, however, Intersil’s unique circuits

allow the threshold to be reprogrammed to meet custom

requirements or to fine-tune the threshold for applications

requiring higher precision.

Features

• Selectable watchdog timer

• Low VCC detection and reset assertion

- Five standard reset threshold voltages

- Re-program low VCC reset threshold voltage using

special programming sequence

- Reset signal valid to VCC = 1V

• Determine watchdog or low voltage reset with a volatile

flag bit

• Long battery life with low power consumption

- <50µA max standby current, watchdog on

- <1µA max standby current, watchdog off

- <400µA max active current during read

• 32kbits of EEPROM

• Built-in inadvertent write protection

- Power-up/power-down protection circuitry

- Protect 0, 1/4, 1/2 or all of EEPROM array with Block

Lock™ protection

- In circuit programmable ROM mode

• 2MHz SPI interface modes (0,0 and 1,1)

• Minimize EEPROM programming time

- 32-byte page write mode

- Self-timed write cycle

- 5ms write cycle time (typical)

• 2.7V to 5.5V and 4.5V to 5.5V power supply

operation

• Available packages

- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP

• Pb-free (RoHS compliant)

Block Diagram

SCK

CS/WDI

VCC

WATCHDOG TRANSITION

DETECTOR

PROTECT LOGIC

DATA

COMMAND

DECODE AND

CONTROL

LOGIC

VCC THRESHOLD

RESET LOGIC

STATUS

8kBITS

16kBITS

VTRIP

WATCHDOG

TIMER RESET

RESET AND

WATCHDOG

TIMEBASE

POWER-ON AND

LOW VOLTAGE

RESET

GENERATION

RESET/RESET

X5323 = RESET

X5325 = RESET

FN8131 Rev 3.00

December 9, 2015

Page 1 of 19

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X5323, X5325 (Replaces X25323, X25325)

Ordering Information

PART NUMBER

PART MARKING

VCC RANGE VTRIP RANGE TEMP RANGE

(V) (V) (°C)

PACKAGE

RESET (Active Low)

X5323PZ-4.5A (Note)

(No longer available, recommended

replacement: X5323S8Z-4.5A)

X5323P ZAL

4.5 to 5.5

4.5 to 4.75

0 to +70 8 Ld PDIP** (Pb-free)

X5323PIZ-4.5A (Note)

(No longer available, recommended

replacement: X5323S8IZ-4.5A)

X5323P ZAM

-40 to +85 8 Ld PDIP** (Pb-free)

X5323S8Z-4.5A (Note)

X5323 ZAL

0 to +70 8 Ld SOIC (Pb-free)

X5323S8IZ-4.5A* (Note)

X5323 ZAM

-40 to +85 8 Ld SOIC (Pb-free)

X5323V14-4.5A

X5323 VAL

0 to +70 14 Ld TSSOP

X5323PZ (Note)

(No longer available, recommended

replacement: X5323S8Z)

X5323P Z

4.5 to 5.5

4.25 to 4.5

0 to +70 8 Ld PDIP** (Pb-free)

X5323PIZ (Note)

(No longer available, recommended

replacement: X5323S8IZ)

X5323P ZI

-40 to +85 8 Ld PDIP** (Pb-free)

X5323S8Z* (Note)

X5323 Z

0 to +70 8 Ld SOIC (Pb-free)

X5323S8IZ* (Note)

X5323 ZI

-40 to +85 8 Ld SOIC (Pb-free)

X5323PZ-2.7A (Note)

(No longer available, recommended

replacement: X5323S8Z-2.7A)

X5323P ZAN

2.7 to 5.5

2.85 to 3.0

0 to +70 8 Ld PDIP** (Pb-free)

X5323PIZ-2.7A (Note)

(No longer available, recommended

replacement: X5323S8IZ-2.7A)

X5323P ZAP

-40 to +85 8 Ld PDIP** (Pb-free)

X5323S8Z-2.7A* (Note)

X5323 ZAN

0 to +70 8 Ld SOIC (Pb-free)

X5323S8IZ-2.7A* (Note)

X5323 ZAP

-40 to +85 8 Ld SOIC (Pb-free)

X5323PZ-2.7 (Note)

(No longer available, recommended

replacement: X5323S8Z-2.7)

X5323P ZF

2.7 to 5.5

2.55 to 2.7

0 to +70 8 Ld PDIP** (Pb-free)

X5323PIZ-2.7 (Note)

(No longer available, recommended

replacement: X5323S8IZ-2.7)

X5323P ZG

-40 to +85 8 Ld PDIP** (Pb-free)

X5323S8Z-2.7* (Note)

X5323 ZF

0 to +70 8 Ld SOIC (Pb-free)

X5323S8IZ-2.7* (Note)

X5323 ZG

-40 to +85 8 Ld SOIC (Pb-free)

RESET (Active High)

X5325S8Z-4.5A (Note)

X5325 ZAL

4.5 to 5.5

4.5 to 4.75

0 to +70 8 Ld SOIC (Pb-free)

X5325S8IZ-4.5A (Note)

X5325 ZAM

-40 to +85 8 Ld SOIC (Pb-free)

X5325S8Z* (Note)

X5325 Z

4.5 to 5.5

4.25 to 4.5

0 to +70 8 Ld SOIC (Pb-free)

X5325S8IZ* (Note)

X5325 ZI

-40 to +85 8 Ld SOIC (Pb-free)

X5325S8Z-2.7A (Note)

X5325 ZAN

2.7 to 5.5

2.85 to 3.0

0 to +70 8 Ld SOIC (Pb-free)

X5325S8IZ-2.7A (Note)

X5325 ZAP

-40 to +85 8 Ld SOIC (Pb-free)

X5325S8Z-2.7* (Note)

X5325 ZF

2.7 to 5.5

2.55 to 2.7

0 to +70 8 Ld SOIC (Pb-free)

X5325S8IZ-2.7* (Note)

X5325 ZG

-40 to +85 8 Ld SOIC (Pb-free)

*Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications.

**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

FN8131 Rev 3.00

December 9, 2015

Page 2 of 19

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X5323, X5325 (Replaces X25323, X25325)

Pinouts

X5323, X5325

(8 LD SOIC, PDIP)

TOP VIEW

CS/WDI

VSS

8 VCC

7 RESET/RESET

6 SCK

5 SI

CS/WDI

VSS

X5323, X5325

(14 LD TSSOP)

TOP VIEW

1 14

2 13

3 12

4 11

5 10

VCC

RESET/RESET

SCK

Pin Descriptions

PIN NUMBER PIN NUMBER

(SOIC/PDIP)

TSSOP

PIN NAME

PIN FUNCTION

1 1 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.

CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation

after power-up, a HIGH to LOW transition on CS is required.

Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The

absence of a HIGH to LOW transition within the watchdog time out period results in

RESET/RESET going active.

2 2 SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

5 8 SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),

addresses and data MSB first.

6 9 SCK Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK

changes the data output on the SO pin.

3 6 WP Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the watchdog timer control and the memory write protect bits.

4 7 VSS Ground

8 14 VCC Supply Voltage

7 13 RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active

RESET

whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above

the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is

enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out

period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-

up at about 1V and remains active for 200ms after the power supply stabilizes.

3 to 5,10 to 12 NC No internal connections

FN8131 Rev 3.00

December 9, 2015

Page 3 of 19

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X5323, X5325 (Replaces X25323, X25325)

Principles of Operation

Power-on Reset

Application of power to the X5323/X5325 activates a power-on

reset circuit. This circuit goes active at about 1V and pulls the

RESET/RESET pin active. This signal prevents the system

microprocessor from starting to operate with insufficient voltage

or prior to stabilization of the oscillator. As long as

RESET/RESET pin is active, the device will not respond to any

Read/Write instruction. When VCC exceeds the device VTRIP

value for 200ms (nominal) the circuit releases RESET/RESET,

allowing the processor to begin executing code.

Low Voltage Monitoring

During operation, the X5323/X5325 monitors the VCC level and

asserts RESET/RESET if supply voltage falls below a preset

minimum VTRIP. The RESET/RESET signal prevents the

microprocessor from operating in a power fail or brown-out

condition. The RESET/RESET signal remains active until the

voltage drops below 1V. It also remains active until VCC returns

and exceeds VTRIP for 200ms.

Watchdog Timer

The watchdog timer circuit monitors the microprocessor activity

by monitoring the WDI input. The microprocessor must toggle the

CS/WDI pin periodically to prevent a RESET/RESET signal.

The CS/WDI pin must be toggled from HIGH to LOW prior to

the expiration of the watchdog time out period. The state of two

nonvolatile control bits in the status register determine the

watchdog timer period. The microprocessor can change these

watchdog bits, or they may be “locked” by tying the WP pin

LOW and setting the WPEN bit HIGH.

VCC Threshold Reset Procedure

The X5323/X5325 has a standard VCC threshold (VTRIP)

voltage. This value will not change over normal operating and

storage conditions. However, in applications where the

standard VTRIP is not exactly right, or for higher precision in the

VTRIP value, the X5323/X5325 threshold may be adjusted.

Setting the VTRIP Voltage

This procedure sets the VTRIP to a higher voltage value. For

example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V,

this procedure directly makes the change. If the new setting is

lower than the current setting, then it is necessary to reset the

trip point before setting the new value.

and pulse CS/WDI LOW then HIGH. Remove VP and the

sequence is complete.

SCK

FIGURE 1. SET VTRIP VOLTAGE

Resetting the VTRIP Voltage

This procedure sets the VTRIP to a “native” voltage level. For

example, if the current VTRIP is 4.4V and the VTRIP is reset, the

new VTRIP is something less than 1.7V. This procedure must

be used to set the voltage to a lower value.

To reset the VTRIP voltage, apply a voltage between 2.7V and

5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, and the

SCK pin HIGH. RESET/RESET and SO pins are left

unconnected. Then apply the programming voltage VP to the

SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP

and the sequence is complete.

SCK VCC

FIGURE 2. RESET VTRIP VOLTAGE

To set the new VTRIP voltage, apply the desired VTRIP

threshold to the VCC pin and tie the CS/WDI pin and the WP

pin HIGH. RESET/RESET and SO pins are left unconnected.

Then apply the programming voltage VP to both SCK and SI

FN8131 Rev 3.00

December 9, 2015

Page 4 of 19

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X5323, X5325 (Replaces X25323, X25325)

NEW VCC APPLIED =

OLD VCC APPLIED + ERROR

VTRIP PROGRAMMING

EXECUTE

RESET VTRIP

SEQUENCE

SET VCC = VCC APPLIED =

DESIRED VTRIP

EXECUTE

SET VTRIP

SEQUENCE

APPLY 5V TO VCC

DECREMENT VCC

(VCC = VCC - 10mV)

NEW VCC APPLIED =

OLD VCC APPLIED - ERROR

EXECUTE

RESET VTRIP

SEQUENCE

NO RESET PIN

GOES ACTIVE?

YES

ERROR  EMAX

MEASURED VTRIP -

DESIRED VTRIP

ERROR EMAX

EMAX = MAXIMUM DESIRED ERROR

ERROR < EMAX

DONE

FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART

VTRIP

ADJ.

4.7k

PROGRAM

2 X5323, 7

3 X5325 6

FN8131 Rev 3.00

December 9, 2015

10k

FIGURE 4. SAMPLE VTRIP RESET CIRCUIT

NC 4.7k

RESET

RESET VTRIP

TEST VTRIP

SET VTRIP

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