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DATASHEET
ISL70024SEH, ISL73024SEH
200V, 7.5A Enhancement Mode GaN Power Transistor
FN8976
Rev.4.00
Feb 8, 2019
The ISL70024SEH and ISL73024SEH are 200V
N-channel enhancement mode GaN power transistors.
These GaN FETs have been characterized for destructive
Single Event Effects (SEE) and tested for Total Ionizing
Dose (TID) radiation up to 100krad(Si) High Dose Rate
(HDR) and 75krad(Si) Low Dose Rate (LDR).
Applications for these devices include commercial
aerospace, medical, and nuclear power generation.
GaN’s exceptionally high electron mobility and low
temperature coefficient allows for very low rDS(ON),
while its lateral device structure and majority carrier
diode provide exceptionally low QG and near zero QRR.
The end result is a device that can operate at a higher
switching frequency with more efficiency while reducing
the overall solution size.
By combining the exceptional performance of the GaN
FET in a hermetically sealed Surface Mount Device
(SMD) package with manufacturing in a
MIL-PRF-38535 like flow results in best-in-class power
transistors that are ideally suited for high reliability
applications.
Related Literature
For a full list of related documents, visit our website:
ISL70024SEH, ISL73024SEH device pages
Features
Very low rDS(ON) 45mΩ (typical)
Ultra low total gate charge 2.5nC (typical)
• SEE tolerance (VDS = 160V, VGS = 0V)
• Characterized at LET 86MeV•cm2/mg
• Radiation hardness assurance testing (lot-by-lot)
• High dose rate (50-300rad(Si)/s): 100krad(Si)
• Low dose rate (0.01rad(Si)/s): 75krad(Si)
• Ultra small hermetically sealed 4 Ld Surface Mount
Device (SMD) package
• Package area: 42mm2
• Full military-temperature range operation
• TA = -55°C to +125°C
• TJ = -55°C to +150°C
Applications
• Switching regulation
• Motor drives
• Relay drives
• Inrush protection
• Down hole drilling
• High reliability industrial
Figure 1. ISL70024SEH 4 Ld SMD Package
FN8976 Rev.4.00
Feb 8, 2019
140
120
ID = 0.8A
ID = 4.0A
ID = 2.4A
ID = 5.6A
100 ID = 7.2A
80
60
40
20
0
2.5
3.0 3.5 4.0 4.5
Gate-Source Voltage (V)
Figure 2. On-State Resistance (+25°C)
5.0
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ISL70024SEH, ISL73024SEH
1. Overview
1. Overview
1.1 Ordering Information
Ordering Part Number (Note 1)
Radiation Hardness
(Total Ionizing Dose)
Temperature
Range (°C)
Package
(RoHS Compliant)
Package
Drawing
ISL70024SEHML
HDR to 100krad(Si)
LDR to 75krad(Si)
-55 to +125
4 Ld SMD
J4.A
ISL73024SEHML
LDR to 75krad(Si)
-55 to +125
4 Ld SMD
J4.A
ISL70024SEHMX
HDR to 100krad(Si)
LDR to 75krad(Si)
-55 to +125
Die
-
ISL73024SEHMX
LDR to 75krad(Si)
-55 to +125
Die
-
ISL70024SEHX/SAMPLE (Note 2)
N/A
+25 Die -
ISL73024SEHX/SAMPLE (Note 2)
N/A
+25 Die -
ISL70024SEHL/PROTO (Note 2)
N/A
-55 to +125
4 Ld SMD
J4.A
ISL73024SEHL/PROTO (Note 2)
N/A
-55 to +125
4 Ld SMD
J4.A
ISL70040SEHEV3Z (Note 3)
Evaluation board with the ISL70040SEH low-side driver and ISL70024SEH 200V GaN FET
ISL73040SEHEV4Z (Note 3)
Half bridge power stage using the ISL73040SEH, ISL73024SEH, and the ISL71610M
Notes:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
2. The /PROTO and /SAMPLE parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
These parts are intended for engineering evaluation purposes only. The /PROTO and /SAMPLE parts meet the electrical limits and
conditions across the temperature range specified in this datasheet and are of the same form and fit as the
ISL70024SEHML/ISL73024SEHML devices. The /PROTO and /SAMPLE parts do not come with a Certificate of Conformance (C of
C) and have no accompanying data or documentation.
3. Evaluation boards use the /PROTO parts and /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event
Effect (SEE) immunity.
Part Number
ISL70024SEH
ISL73024SEH
ISL70023SEH
ISL73023SEH
Table 1. Key Differences Between Family of Parts
Breakdown Voltage
Radiation Assurance
200V
HDR to 100krad(Si)
LDR to 75krad(Si)
200V
LDR to 75krad(Si)
100V
HDR to 100krad(Si)
LDR to 75krad(Si)
100V
LDR to 75krad(Si)
FN8976 Rev.4.00
Feb 8, 2019
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ISL70024SEH, ISL73024SEH
1.2 Pin Configuration
(4) G
(3) D
4 Ld SMD
1. Overview
(1) S
(2)
SUB
Pin #1 Index Area
(1) S
Top View
(2) SUB
(4)
G
(3) D
Bottom View
Note: The ESD triangular mark indicates Pin #1. It is a part of the device marking
and is placed on the lid in the quadrant where Pin #1 is located.
1.3 Pin Descriptions
Pin Number
1
2
3
4
NA
Pin Name
Description
S Source connection for the GaN FET.
SUB
Substrate connection for the GaN FET which is internally shorted in to source. Tie this pin to source on
the PCB.
D Drain connection for the GaN FET.
G Gate connection for the GaN FET. Minimize trace inductance from driver to reduce over-stressing the
gate.
Lid Internally tied to the source pin.
FN8976 Rev.4.00
Feb 8, 2019
Page 3 of 13

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ISL70024SEH, ISL73024SEH
2. Specifications
2. Specifications
2.1 Absolute Maximum Ratings
Parameter
Minimum
Maximum
Unit
VDS
VDS (Note 4)
VGS
ESD Rating (Drain-to-Source)
0 200
0 160
-4 6
Value
V
V
V
Unit
Human Body Model (Tested per MIL-STD-883 TM3015)
2 kV
Machine Model (Tested per JESD22-A115C)
200 V
Charged Device Model (Tested per JS-002-2014)
750 V
ESD Rating (Gate-to-Source)
Value
Unit
Human Body Model (Tested per MIL-STD-883 TM3015)
500 V
Machine Model (Tested per JESD22-A115C)
200 V
Charged Device Model (Tested per JS-002-2014)
750 V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can
adversely impact product reliability and result in failures not covered by warranty.
Note:
4. Tested in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC).
2.2 Thermal Information
ISL70024SEH, ISL73024SEH in SMD Package J4.A
Thermal Resistance
Typical
Maximum
Unit
θJA (Note 5)
42.0 - °C/W
θJC (Note 6)
18.7 23.4 °C/W
Notes:
5. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach”
features. See TB379.
6. For θJC, the “case temp” location is on the solder terminations adjacent to the center of the package underside.
Parameter
Maximum Junction Temperature
Storage Temperature Range
Minimum
-
-65
Maximum
+150
+150
Unit
°C
°C
2.3 Recommended Operating Conditions
Parameter
Temperature
VDS
ID (VGS = 5.0V, TC = +25°C) (Note 7)
ID (VGS = 5.0V, TC = +105°C) (Note 7)
Note:
7. TJ = +150°C. Current limited by package constraints.
Minimum
-55
0
0
0
Maximum
+125
160
7.5
4.5
Unit
°C
V
A
A
FN8976 Rev.4.00
Feb 8, 2019
Page 4 of 13

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ISL70024SEH, ISL73024SEH
2. Specifications
2.4 Electrical Specifications
Unless otherwise noted, VDS = 160V. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total
ionizing dose of 100krad(Si) with exposure at a high dose rate of 50-300rad(Si)/s; or over a total ionizing dose of 75krad(Si) with
exposure at a low dose rate of <10mrad(Si)/s.
Parameter
Symbol
Test Conditions
Min Typ Max
(Note 9) (Note 9) (Note 9) Unit
Static Characteristics
Drain-to-Source Breakdown Voltage
Drain-to-Source Leakage Current
Drain-to-Gate Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
Drain-to-Source ON-Resistance
Source-to-Drain Forward Voltage
Dynamic Characteristics
BVDSS
IDSS
IGSX
IGSS
VGS(th)
rDS(ON)
VSD
VGS = 0V, ID = 125µA
VDS = 160V, VGS = 0V
VDS = 160V, VGS = 0V
VGS = 5V
VGS = -4V
VDS = VGS, ID = 1.5mA
VGS = 5V, ID = 7A
IS = 0.5A, VGS = 0V
200 -
-V
- 1 115 µA
- 1 115 µA
- 0.8 2.5 mA
-100
-20
- µA
0.8 1.4 2.5 V
- 45 110
0.8 1.8 3.5 V
Input Capacitance
CISS VDS = 100V, VGS = 0V (Note 10)
- 270
Output Capacitance
COSS VDS = 100V, VGS = 0V, TA = +25°C
- 150
Reverse Transfer Capacitance
CRSS VDS = 100V, VGS = 0V (Note 10)
-1
Gate Resistance
rG TA = +25°C (Note 10)
- 60
Total Gate Charge
QG VDS = 100V, VGS = 5V, ID = 7A, TA = +25°C
-
2.5
Gate Charge at Threshold
QG(th) VDS = 100V, ID = 7A (Note 10)
- 0.4
Gate-to-Source Charge
QGS VDS = 100V, ID = 7A, TA = +25°C
- 0.8
Gate-to-Drain Charge
QGD VDS = 100V, ID = 7A, TA = +25°C
- 0.6
Output Charge
QOSS VDS = 100V, VGS = 0V (Note 10)
- 23
Notes:
8. Typical values shown are not guaranteed.
9. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C, and +125°C, unless otherwise specified.
10. Limits are established by characterization and/or design and are not tested.
-
200
-
-
5
-
2.0
2.0
-
pF
pF
pF
nC
nC
nC
nC
nC
FN8976 Rev.4.00
Feb 8, 2019
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